Single Ended Outputs Syncronization

Hi,

this is a very difficult problem to solve. Let me give you some options:

1) connect OUT0AP=1Hz to REFAA and OUT1AP to REFB. Measure to phase offset between REFAA and REFB using the skew measurement feature (page 160 in the data sheet). Compensate the phase offset in OUT0A, OUT0B and OUT0C (page 97 in the data sheet). This makes the DPLL0 1Hz outputs to be in phase to DPLL1 1Hz outputs.

Then to maintain this alignment when REFA=10MHz goes invalid, you need to create a second profile for DPLL1 that uses the DPLL0 feedback. In this way, when REFA goes invalid, DPLL1 is cascaded to DPLL0: DPLL0 enters holdover and DPLL1 locks onto DPLL0 feedback and maintains DPLL1 outputs in  phase to DPLL0 outputs.

The problem with all this trouble is that you loose two outputs because you have to connect them to REFAA and REFB. So you remain with only 3 1Hz outputs to distribute.

So I propose a simpler way that also can generate four in phase 1Hz outputs instead:

2) You set DPLL1 to receive 10MHz and create 1Hz clocks. You take OUT1A=1Hz  differential and you bring it to REFB and REFBB. Then you set DPLL0 to lock in internal zero delay onto REFB. In this way, all DPLL0 outputs will be in phase to OUT1B=1Hz (and OUT1A that you used as source to DPLL0).

I tried it on the AD9546 eval board and it worked.

You have to set OUT1A as CML, 7.5mA, modify the eval board for OUT1A to work as CML and change REFB to DC coupled.

You also have to add a OCXO to REFAA, so you can stabilize the system clock wonder. Otherwise the DPLL0 loop will not lock.

Even if REFB becomes invalid, DPLL0 outputs remain in phase to DPLL1 outputs because DPLL0 remains locked onto OUT1A.

Attached is the json file I used. My OCXO was 20MHz.

AD9546_setup_four_1Hz_sync_clocks.json.txt

3) Just take one of DPLL0 outputs and pass them through a fan out buffer. They will be in phase with the error of the fan out buffer propagation delay. Do not use DPLL1 at all

Your json file had the DPLLs working with 50mHz loop bandwidth. Because the reference clock was 50Hz, you can work with 50Hz bandwidth. 

Petre

Hi Petre,

I just realized that there are some details about my system.

I was configured the output channels as 1Hz with the same phase, but I will be create dedicated phase offset among all outputs using offset control register later on.

While system is working with dedicated phase offtests, I will give a sync signal for 3 clock cycles using M-pin and I expect all outputs (channel0 and channel1) start again with dedicated phase offtest which I entered before.

In this scenario, is there any way to do that?

While I was trying you previous answer, could you please help me with this matter?

Thank you,

Oguzhan

HI,

I do believe the first two solutions work with your phase offsets. Just configure the AD9546, introduce the desired phase offsets and then generate Sync All command. This will make the outputs to be generated with the desired phase offsets and then, when the DPLLs have locked, they will also have exactly 1Hz obtained from your 10MHz.

The third solution uses a fan out buffer and this buffer would have to have some kind of phase offset adjustment. To use for example the AD9508, which has such a phase adjustment, you would have to generate 1024Hz clock at its input (which would be phase aligned to the other 1Hz outputs), divide it down 1024 times inside the AD9508 to 1Hz and use the phase offset adjustment that works in steps equal to half a period of 1024Hz. 

Petre