Hi,


AD9577
Recommended for New Designs
The AD9577 provides a multioutput clock generator function,
along with two on-chip phase-locked loop cores, PLL1 and PLL2,
optimized for network clocking...
Datasheet
AD9577 on Analog.com
Hi,


HI,
you already saw that the AD9577 does not like both PLL VCOs set to the same value. The data sheet states it clearly at page 34:

So I propose to use this configuration below, in which PLL2 VCO is at 2200MHz, which may be divided down to obtain 100MHz and 33.33MHz:

I also attach the stp file I created. Just take out the txt extension before loading it into the eval software.
;Header contains information about the setup file and revision <Header> Product = AD9577 FileVersion = 1.0 DecimalSeparator=. ; Used for internationalization </Header> <RegisterMap> &h11,&b00000000 ;00 Hex, 000 Dec (default) &h18,&b00010000 ;10 Hex, 016 Dec &h19,&b00000000 ;00 Hex, 000 Dec (default) &h1A,&b00000000 ;00 Hex, 000 Dec (default) &h1B,&b00000000 ;00 Hex, 000 Dec (default) &h1C,&b00001000 ;08 Hex, 008 Dec &h1D,&b11010000 ;D0 Hex, 208 Dec (default) &h1F,&b00000000 ;00 Hex, 000 Dec (default) &h22,&b01001100 ;4C Hex, 076 Dec &h23,&b01000110 ;46 Hex, 070 Dec &h24,&b00000000 ;00 Hex, 000 Dec (default) &h25,&b01001011 ;4B Hex, 075 Dec &h26,&b11001011 ;CB Hex, 203 Dec &h27,&b00000000 ;00 Hex, 000 Dec (default) &h29,&b10000000 ;80 Hex, 128 Dec (default) &h2A,&b00000000 ;00 Hex, 000 Dec (default) &h2B,&b00000000 ;00 Hex, 000 Dec (default) &h2C,&b00000000 ;00 Hex, 000 Dec (default) &h30,&b00010100 ;14 Hex, 020 Dec (default) &h31,&b10000100 ;84 Hex, 132 Dec (default) &h32,&b10000101 ;85 Hex, 133 Dec (default) &h33,&b00010110 ;16 Hex, 022 Dec (default) &h34,&b00000000 ;00 Hex, 000 Dec (default) &h35,&b00000000 ;00 Hex, 000 Dec (default) &h36,&b00000000 ;00 Hex, 000 Dec (default) &h37,&b10000110 ;86 Hex, 134 Dec (default) &h38,&b01000110 ;46 Hex, 070 Dec (default) &h39,&b01110101 ;75 Hex, 117 Dec (default) &h3A,&b00000000 ;00 Hex, 000 Dec (default) &h3B,&b00000000 ;00 Hex, 000 Dec (default) &h3D,&b00000000 ;00 Hex, 000 Dec (default) &h40,&b00000000 ;00 Hex, 000 Dec (default) </RegisterMap> <PinStates> REFSEL=&h1 MARGIN=&h0 SSCG=&h0 MAX_BW=&h0 </PinStates> <SoftwareSettings> CrystalIndex=1 ; External crystal being used (0=19.44MHz, 1=25MHz, 2=27MHz) ExternalRefclk=25.00000 ; External REFCLK frequency in MHz </SoftwareSettings>
If I understand correctly what you are saying, you have your own AD9577 board (not an evaluation board) and you manage this chip with a FPGA and the chip, once programmed, the outputs do not have the expected frequency. It seems the PLLs did not lock, so you may not have calibrated the VCOs.
To initialize correctly the AD9577, follow the procedure from the data sheet, page 41:

Also, read back the registers you wrote, so you can understand if the I2C read and write FPGA operations work.
Petre
Hi, Petre
Hi,
I'm sorry to say, but I do not support this ADS7-V2EBZ board. You should contact people that support it on another forum (I see people use high speed ADC and high speed DAC forums with questions about this board).
I do not have an HDL project for the AD9577.
Petre