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Noise floor is very high in the AD9523-1 clock output

Category: Hardware
Product Number: AD9523-1

Hello,

"AD9523 Regmap File"
"Rev.","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","10000001","81"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","00101000","28"
"0011","00000000","00"
"0012","00101000","28"
"0013","00000000","00"
"0014","00000001","01"
"0015","00000000","00"
"0016","00101000","28"
"0017","00000000","00"
"0018","00001100","0C"
"0019","00011111","1F"
"001A","00011010","1A"
"001B","00010111","17"
"001C","10010000","90"
"001D","00000000","00"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","00000111","07"
"00F1","10000111","87"
"00F2","00010011","13"
"00F3","00000010","02"
"00F4","01000000","40"
"00F5","00000000","00"
"00F6","00000000","00"
"00F7","00000001","01"
"00F8","00000000","00"
"00F9","00000000","00"
"00FA","00000000","00"
"0190","01110011","73"
"0191","00001001","09"
"0192","00000100","04"
"0193","00100000","20"
"0194","00011111","1F"
"0195","00000100","04"
"0196","01101000","68"
"0197","01100011","63"
"0198","00000000","00"
"0199","01001001","49"
"019A","00001001","09"
"019B","00000000","00"
"019C","01001001","49"
"019D","00001001","09"
"019E","00000000","00"
"019F","01001001","49"
"01A0","00001001","09"
"01A1","00000000","00"
"01A2","01001001","49"
"01A3","00001001","09"
"01A4","00000100","04"
"01A5","01001001","49"
"01A6","01100011","63"
"01A7","00000000","00"
"01A8","01001001","49"
"01A9","01100011","63"
"01AA","00000000","00"
"01AB","01001001","49"
"01AC","01100011","63"
"01AD","00000000","00"
"01AE","01001001","49"
"01AF","01100011","63"
"01B0","00000000","00"
"01B1","01001001","49"
"01B2","01100011","63"
"01B3","00000000","00"
"01B4","01001001","49"
"01B5","00001001","09"
"01B6","00000000","00"
"01B7","01010011","53"
"01B8","00001001","09"
"01B9","00000000","00"
"01BA","00000000","00"
"01BB","00000000","00"
"022C","00000000","00"
"022D","00000000","00"
"022E","00000000","00"
"022F","00000000","00"
"0230","00000000","00"
"0231","00000001","01"
"0232","00001101","0D"
"0233","00000000","00"
"0234","00000001","01"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00101011","2B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000011","03"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"

attached text file is what I configured to AD9523-1. REF A,REF B are of 100MHz. and I'm feeding REF B from the signal generator 100MHz clock with 6dBm input power. I took the screenshot of 100MHz clock output from the AD9523-1 and here I'm attaching that. noise floor at 100MHz has lifted very highly. How to reduce the noise floor.
for your reference I'm attaching the schematic also.  . I'm also attaching the screenshot of 100MHz clock, how we require.
please help us to make the AD9523-1 clock like this.

Parents
  • also a small help, can you please send the screenshot of AD9523-1's eval board 100 MHz clock out.

  • Hi,

    I looked at the stp file you sent. The schematic shows REFA as being a differential LVDS, AC coupled. In the stp file,  REFA is not enabled as differential, but as single ended on REFA negative. Why?

    REFB is enabled as single ended on negative pin. 

    You say you used REFB as reference. Please send me a scope capture of it.

    The zero delay differential mode is enabled and on the board the OUT0 to ZD_IN is AC coupled. But in the stp file, OUT0 is off. So how is the AD9523-1 is supposed to work?

    Did PLL1 and PLL2 lock? 

    I cannot test your configuration in the lab because I do not have a 100MHz VCXO. I'll make a note to get some measurements on an eval board with the signal analyzer and the phase noise analyzer and get back to you.

    I recommend looking at the figures 11 and 12 in the data sheet, page 18 to see how the outputs should look.

    Petre

  • Hi again,

    I created a configuration in ADIsimCLK that takes an ideal 100MHz clock reference and it passes it through the AD9523-1. I then used the Crystek CVHD-950 of 100MHz. I then set up several 100MHz outputs, each with a different driver: LVPECL, LVDS, CMOS, HSTL. The tool provides the expected phase noise for each of these choices. If you had a phase noise analyzer, we could compare your results against these. 

    I attach the report: 

    AD9523_1_setup.clk analysed at Wed Jan 29 16:31:23 2025 
     
    Clock Chip is AD9523-1 
    VCO is AD9523-1 
    Reference is custom 
     
     
    PLL1 Loop Filter specified by: Phase Margin 
    	Design Objective:  Loop Bandwidth: 30.0 Hz   Phase Margin: 75.0 deg 
    	Simulation Result: Loop Bandwidth: 31.04 Hz   Phase Margin:  82.9 deg 
     
    PLL2 Loop Filter specified by: Phase Margin 
    	Design Objective:  Loop Bandwidth:  450kHz   Phase Margin: 75.0 deg 
    	Simulation Result: Loop Bandwidth: 445.8kHz   Phase Margin:  74.5 deg 
     
    Power Dissipation Estimate 
    Core			 325mW 
    Ref single		4.0mW 
    OUT0			48.6mW 
    OUT1			30.4mW 
    OUT2			35.9mW 
    OUT3			57.8mW 
    OUT4			92.1mW 
    OUT5			92.1mW 
    OUT6			92.1mW 
    OUT7			92.1mW 
    OUT8			92.1mW 
    OUT9			92.1mW 
    OUT10			92.1mW 
    OUT11			92.1mW 
    OUT12			92.1mW 
    OUT13			92.1mW 
    PLL1_OUT		24.4mW 
    Total Power		1.45 W 
     
    OUT0:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      SONET OC-1 Jitter =  110fs rms 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT0 is 0s 
     
    OUT1:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT1 is 0s 
     
    OUT2:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT2 is 0s 
     
    OUT3:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT3 is 0s 
     
    OUT4:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT4 is 0s 
     
    OUT5:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT5 is 0s 
     
    OUT6:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT6 is 0s 
     
    OUT7:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT7 is 0s 
     
    OUT8:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT8 is 0s 
     
    OUT9:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT9 is 0s 
     
    OUT10:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT10 is 0s 
     
    OUT11:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT11 is 0s 
     
    OUT12:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT12 is 0s 
     
    OUT13:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT13 is 0s 
     
    PLL1_OUT:  
      Frequency: 50.0000MHz 
      Broadband Jitter (>1kHz) =  180fs rms 
        SNR =  78.94dB  ENOB =  13.16bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 39.0fs rms 
        Phase Jitter EVM = 0.0012 %rms 
        Phase Jitter = 0.00070 degrees rms 
        ACI / ACR = -101.3dBc 
      Delay from Ref to PLL1_OUT is 0s 
     
    Frequency Domain Analysis of PLL2 
      Analysis at PLL output frequency of 3.00GHz 
     
    Phase Noise Table  
    Freq	Total	VCO	Ref	Chip	Filter 
     100 	-76.92 	-149.1 	-77.61 	-85.25 	-180.2  
    1.00k	-93.45 	-135.1 	-101.3 	-94.23 	-160.2  
    10.0k	-105.8 	-121.3 	-125.4 	-106.0 	-140.4  
     100k	-111.5 	-115.7 	-129.8 	-113.9 	-126.9  
    1.00M	-124.4 	-132.3 	-139.2 	-126.1 	-133.4  
     
           ----    End of Frequency Domain Results   ---- 
     
    Transient Analysis of PLL2 
      Power up transient to frequency of 3.00GHz 
      Simulation run for  349us 
     
    Frequency Locking 
      Time to lock to 1.00kHz is  330us 
      Time to lock to 10.0 Hz is  344us 
     
    Phase Locking (VCO Output Phase) 
      Time to lock to 10.0 deg is  324us 
      Time to lock to 1.00 deg is  330us 
     
    Lock Detect Threshold 
      Lock Detect output did not pass 2.50 V 
     
           ----    End of Time Domain Results   ---- 
     
           ----    Summary of Settings   ---- 
     
     
    Reference	custom 
       Frequency	 100MHz 
       Phase Noise	None 
     
    PLL1	 
       Design Freq	 100MHz 
       VCO	CVHD-950 
          Tuning Law	Datasheet Kv 
             Kv	1.21kHz/V 
             V1	0V 
             F1	99.998MHz 
             V2	3.30 V 
             F2	100.002MHz 
          Input Cap. (Ct)	0F 
          Phase Noise	Table 
             PN Floor	-162 dBc/Hz 
       Dividers	 
          R1	1 
          N1	1 
       Phase Detector	 100MHz 
          Icp	16.0uA 
          V max	3.30V 
          V min	0V 
          ABP Pulse	0s 
          PN Floor	-219dBc/Hz 
       Loop Filter	AD952x LF 
          Specify:	Phase Margin 
          Loop Bandwidth	30.0 Hz 
          Phase Margin	75.0 deg 
          Zero Loc.	3.38 Hz 
          Pole Loc.	 266 Hz 
          Last Pole Loc.	 799 Hz 
          Cpole1	1.50nF 
          Rzero	10.0k 
          Cext	4.70uF 
          Rpole2	 165k 
          Cpole2	 337pF 
          Rext	0 
       FreqDomain 
          Min Freq	1.00 Hz 
          Max Freq	1.00MHz 
          Pts per Decade	10 
          Analysis at	 100MHz 
     
    PLL2 
       PLL Setup 
          Min Freq	3.00GHz 
          Max Freq	3.00GHz 
          PD Freq.	 200MHz 
             Ref Divider	1 
             Ref Doubler	enabled 
          Design Freq	3.00GHz 
       VCO	AD9523-1 
          Tuning Law	Multiband 
          Phase Noise	Table 
             PN Floor	-173 dBc/Hz 
       Chip - PLL	AD9523-1 
          Main Divider 
             Prescaler P	4 
             Min ctgs div.	Not Used 
             Counter Bits	13 
             Min value	1 
             Max Freq.	3.10GHz 
             Max PS Out Freq	Not Used 
             Min Freq.	2.93GHz 
          Ref Divider 
             Counter Bits	10 
             Min value	0.500 
             Max Freq.	 400MHz 
             Min Freq.	0Hz 
          Phase Detector	Charge Pump 
             CP Current	 515uA 
             Polarity	positive 
             Leakage	0A 
             AB Pulse	Not Used 
             Vsupply	3.30 V 
             Vmin	0V 
             Vmax	3.30 V 
             Max Freq.	 250MHz 
             PN Floor	-226 dBc/Hz 
          Lock Detect	None 
       Loop Filter	AD952x LF 
          Specify:	Phase Margin 
          Loop Bandwidth	 450kHz 
          Phase Margin	75.0 deg 
          Zero Loc.	50.7kHz 
          Pole Loc.	4.00MHz 
          Last Pole Loc.	12.0MHz 
          Cpole1	8.00pF 
          Rzero	1.85k 
          Cext	1.80nF 
          Rpole2	 900  
          Cpole2	16.0pF 
          Rext	0 
       TimeDomain 
          Type	Power On 
          Frequency	3.00GHz 
          Stop Time	 349us 
          Max Time Step	 250ps 
          VCO Autocal.	enable 
     
     
     
     
     
    Clock Dist.	 
       VCO Freq	3.00GHz 
       M1 Div Output	1.00GHz 
          M1 Div	3 
       M2 Div Output	1.00GHz 
          M2 Div	3 
       OUT0	OUT0 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT1	OUT1 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVDS 
             Output Current	3.50mA 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT2	OUT2 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	CMOS 
             Max Frequency	 250MHz 
       OUT3	OUT3 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	HSTL 
             Output Current	8.00mA 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT4	OUT4 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT5	OUT5 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT6	OUT6 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT7	OUT7 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT8	OUT8 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT9	OUT9 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT10	OUT10 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT11	OUT11 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT12	OUT12 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT13	OUT13 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       PLL1_OUT	PLL1_OUT 
          Frequency	50.0MHz 
          Divider	 
             div N	2 
          Output	CMOS 
             Max Frequency	 250MHz 
     
    Timing An.	 
       Start Time	-1.00ns 
       Stop Time	50.0ns 
     
    FreqDomain 
       Min Freq	1.00kHz 
       Max Freq	 100MHz 
       Pts per Decade	10 
       Analysis at	3.00GHz 

    This is the phase noise you should obtain for a LVPECL 100MHz output:

    This is for 100MHz LVDS:

    This is for 100MHz CMOS:

    This is for 100MHz HSTL:

    This will give you the characteristics of your 100MHz outputs.

    I attach the ADIsimCLK file (take out txt extension before loading it).

    AD9523_1_setup.clk.txt

    I also attach the lib files you need to install in this folder (maybe two of them come already installed, just check first). You need to first take out txt extension, then unzip them, then copy the content into this folder: C:\ProgramData\Applied Radio Labs\ADIsimCLK\lib\VCO

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    }�P8 6�g<����ζU>xNZ��s���:�D�P�6I�ghѿc~Άm� Qh+����ӂ��4g`9%������|̀P�c���e9���&��;mS�'����@c;7'3Q�P�!-n��̜ۢ���4��v��L��-�0��x���ϓ3�t��9�Bf�X��;&{��4��6�'s��J�'0S�f�i��%��&�Y�_1 ���N���'�:z��ł\@%��:>��K�O+}>���$5 ��<��~o3I�2�ՃIʧ1	�zWWA���}3&I�aLBW��>!m�I����ep(�|� ��r	���%9���M
    �Krk��/.}�$�U:ϛRHT�2�M�rӪ
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    \�ykv.��v�tI'm��,X��DO�	²�P_�NF����r�6���n�I��S:�2��g@���K�:!��[�ۤF?�@#Q��	�`���ѷ8�9ɫݖ�7b�kߙ^d�!|��^����Ia���u�@E�2?��
    Y�m�Y ۅYy#���U����A���X��No��ѶE�\����j�+��P;�i��À�[�h7��HԀr������ч��g�c��g�V�U�/K�[C��c<��~��ptB�gw0���3��'B1AV:��������'�hJWDS���.w�_��1�Z�	��C��	�k0��9��n��^���0#	�k�f@�O��e(���>�A�
    ӪzTY�y���M�I�(��g��	�نb�����v�z��7���&�[4��͖��{2ΐ]o��W� (vޙy 'Y�^���	��P#��m��8\���Z����@�]�סL���z tv���@2��n*~�j���[9��>��s��9�oG��Q?B2�9�0 3��
    |�X�t1���;���TG/�p;5a|Sx�@Ng_�q�F<4��0ta�zB2C�*��Y-D�����.���zP�r|�f�f�Nb��B̖���ã��c1..I#�$�1g��^�D���$��~��41��Sh����H�zt���z�7���x��V�7�^��l��^�!���2ҼȍA�ac`�j��LGB%�X4��¨�)$
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    PGW�+��5H�x�`�x��=�}D�h^=�6�	�:���0&O,i6ϋ�vU�	-(g���b�)������t�Fg]�0������:�݆J��j��B�2�T�Љ�����:Q�1)4YW��b�$��]ŀW�H�X��/N�:� y���M�$�(,�9�QJv�m��*6̌y��zC7�)݀v	ݖn@��y�/!�+�����7L�y�u�YҘ���qh�a��p�k������x&�A�
    �m;�`U?�!ԕ7�e艈1��9�!}h�ИʴÅ-�2̼8)��jQ������	#OG��~��A�I:����r��xW�������l�v��(P���f���A��i�Lh�O+P�,���3~ؖPۊ?gs�����������2�;�6����v�ڜʹ��������\Q�Fcԋv�)M�C=�|)�a�C=p��pE�@�{�a��u)Tw臒5\�6�L������mu��3�b@��T؛~�I�WX��m/�S�	���i����V)DsC�"|\	�d+d�S�VL�|�?qJd�l|�N$	�V�P�Kj���˃h�a�i%�!T�|ȉ:i%E��lP-�+*b�C�F#�{
    ����K�XE��TH�!�H��ׯx�k8rûd�4������2�}D��W��rW��qʝ����ޠ���a^�+h��A2�i��p�@�x?��}dD$6Ar���A3E�CR��T $�\�6M�u�&]�&M�xỜԱ��k��Uɀ�2*�U��!/\T��>^9�`X�̋�2��]�C�d���P���n&M��[B��-����%/�;.�c��?�r�Gl��7��-�0n��%�Ѓ�J0�o#�9x$���0���]����`IPy�W�ZR�YCm犉��|r:���:,W�=�)�02�I�������a[z*Q��x�t@"e��v�t�ZB��+��3zU?���΁��:��
    �%�8k�F�5j!�>�Z����zqj�~�'WґɬF�RåE���2�
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    MC����jfׇm����ذ��0��TS袵��=�bs(�R�����N���E�Ll&)%�SX����Ԇ�)����X\8q
    &p��}M�aMn�d����V��{n'�r������:ꈀ��j��VfOf��\g�_-�����X=y�k�,x�.�#��]�,轖��т�.<a��5(:-�i����GȽ����#�1�Wװ͕�(�`��G5� �.i�Pf��V}5�A��ldC"�ydf�Ѩ��Q�I��|�,}�����̾�U�jYF3U���4q"��zƾz�쫷hq����6(�a���4�����H;Ȣ(�I�ș|�Ț�����V�o��b�B�,?����a$�X��RX�\t�.�Z�	��B|?��dA ����B��6S�Rҁ�y l�Z���v�J���G/�2,�p�iFa����<���+��n�ש��eF�&����i�A��\��R�`�Ah���޳��T�}�ay�3�v:�訲�-�~"�1p�rqJ�ɤ�f.g�9�~�����#����1}/l�l=�r^�F�4��fEV�g�k���!�@*��5 !���z�[�z�� ~3=P2=�c���&��f"�b�8Q3�Πf"B�%�n�M�D�A@�nePQ3,�d5�H�����䕪��$Q�� Ŕ�db��{6b޳��X�"e��Ϲ��"ep�o�q�a�4fY�H�:�#A�5_V�5Y�u3�.����2�,���c[X�PNaWƂ�h<�:K`�O�xl��ũ\���r?i�XZKg��©9�ރgxu\�Le٨˗&�}̾i� i���j��4b
    ����q�����)nZ�Ly2n��{�I����/�>R����X�9��?'i��E+���l�ta"�m3&��t`}�Ue�����` ���E��#h3�3�󰎂w�ZZ�����D]�ɸ)�$W��5�`�aQY���k��*"����lx<���q6�^y"���qA�Ⱦ
    �A���>s�K���qqR�`���l(�k/�H�]<�)��07�@��y׻�vk�*��R�{/��ګ��cE�J�ҧ�J%u����w`.�s��L�1P�)��<5B�4%P6&�00�w�*����C��\�Gڷ���%�nKϜ�I��^I
    ��
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    ��&8��4Jl���d�0�̡�1���%�g��禹'E�5��RU]A��RX�Ϛ]���R;֓u5��)=�n-[a�	$~�k�êe.ɟ�1�E�9@H:�Iex�Ƕ��r�S�C	������÷�^	Pg������۪?:W��x�S&'z���iq
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    �t�A7���<��*�r�������aYs?�P4��t���W"���*�U[��T/�^]��
    �#�k_�M��'`�r��N�)�b��NlۖY�gAw��8L�lC�i5N�n��M�}��J�L��6���s��v��m��B�vm.�n�Ԧ�n����lӜXu�`���h�LvJ��a_�A'su�}��V����ڦ(3b�>g�feZ�
    	5˼++���I@͌h���tl�q�\?����J墑����rNq���,�D�SG����S��
    �:�}'�Ꮦ��`}�*=�m�5G���j)o���,&��TM2��z�5�5X#hx��p���k���#DԸr����wc�Wgc���O0��Dݸ}���-$�a�k����K����Dc�ۤ-m��oSP7�褪�m_)�[d��6@
    }�&��;Ż���@M�'�ڦ��D\�m�2��ST���NI?A@��奍m�P�z���6����eC\���|0�� ��2S�����E}{F6��˜D	� P���������@������HE]��e̊�|,O��*��"l5n3�S,i4��`�Y{�Twj(�g����ЋO���{��P�)��d���HF1�Pa(��l�xp����0���5�LzFk�U�2�X�l՗������rU6�X��{E//änKFq�6��蘎<�p9�0��;m�@�$3/kt�北��z�A��lBd�d��/��N�k�^T}B/2���9U��D��\�{9�e�Y1�5��b��[�UVn�ٺ�Aׂ��Z�i��4!��
    +��H�\E���c�?	p�}eʰ�E�s/�X�1���ӬZ�9����r�4s�斣��T��C�"J�;ֶ�,Yp�	������:@�oY"��ɠ�(hɦ�Š�̜f���A�}P!9Lٝ:��mj���d��)��<���Q�Q��׻��ʣ��lN�^V',��fD����[s��r���2Ul&@�j~Q*d���>�I�;���0��m�]�֍�M�m�2[jy.�E�q�8K�P����!@�C*0n,J#��/SxUJ�P��!j)�7�쥂M:뾕�p�ͽ�Ѓӻ�a�]qE)tf��R����'l#k�94e7��C)�=.~�
    �-�ǟ%��}N˺tR���h�� =`Z-��2Z�T��Rpdg����r�!L��M�Z�!�֠�s"��?����L����e�Y(�9������/Y�v����)��}�P P7�Ot�O��R��/c����#Ď[��8�#D�[3���j��w�])%�X
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    tK���0W?T��fn�����V*=,o�N⊓�NX�iW�$Ҙ5f�	��/W�������#�Tc*�?/�OF����d��>�S�,�7Ȥ5K��λin���/����~c�S��$'���	N�~�W�����u��@�aNv���v(^9f8*D�iN".VC�\�s���4a	��[��l¢�I%���6A�������i�{/T�	�A>y��%�pk�]�r��QƬ�N�,�^��6V�
    ��4<pW��a��k��J	aH�0e��b�qV0ve��+hJ��v\�̥�EI�pn7��ā�8{ܷ|7���x��"86�H8 Z�H����=��ZI��%DC����ڤ�X�J
    eKϥ[l{"�T��W}��PWV����Ǝ�O�����|�^v����#��Ɏ�3�kT�3|Q����6��	�:R��M���zƒ���u�Uǟ�\GP9$og������"�o����!��#ֱ�mQ&)j7��&;uX50C�Q^G�Ӫ��0EkS+����V:u�.A@�O2�J�n�Ӣ�	t�r��d�Lک����T�5Yí$%�v4-X�t��c*�D'�;�D���d����}p3�WKT��'a�DY]��O)�(j����.�~7��u�=����F�\wR&\����C6�G�<7�Ayj�7����_�$a��y���
    �<�R��]�����L�b�`�(���(�*�ktV�N@wsU�,�M�5�(����5���
    X�	h*��r�']����4y�"!���7��:J���Gy�]!�F����M�-m�(2�.`!<C ȟ���]Ɏ)(m�\<�r��.XZ�ܚ�O1 ����iٴ���%��\Ie�̜]� gB����5Mے��/�v�L��D��i ���XP���U�c�M親191MqZm!��4�GR�@ȴn��DO�ʑRUa�B��L�n���b�ܪ�
    �t�W2�>�����]�'��{�h�[(�(�,�>J'����{�pmS����r�r��e�����n�D��;��n�O��
    ~�0/�����w1*����1Os��f�ف���و^�s)�p%=��[\����b�W�@9�R/n��ѩ;�N�n��^zc�]F�j����,[��|�ml�K#L��n›��6��B3�\��Ο#X^��vY�{2�vn�D������`�.�R\*�@��R[<{\f�.� �8����h$R��nНi&�0sV��Id�qh�3�0�t62,�mpK�}r|�24�����ѓ��hյ3��f�2�}|���D8�R��W��%���/�VX������D����ź�_�^I	t>M3�-_�fF���̲[������^��[��dp-�dVA"+ƣ��l1�Y�
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    V?������q�$m���<3�����=���.P0.wȥ���j���q���<��d]�-�ޒLZr�O�*�u��֭I���F��Jtl˝J
    �4�[��˕�����2U��(�\�4!���B��i-i�?'��-�aw�y��E��!�N��b���C8"N���Sy%�)�>G���a�3�H�ed����;��%�y�n0|��-��C��<�Q�H�����`%o�.^���g+��|D��h�,g8q"�>l�j��+���ʙ�F�d�>}%P�y��<3�}tq��|��2w�h�
    =���Y'�:��⍙Z��"�����c)`�pY�ZW&β�f<S��?��-1��"�-�&��
    xK�C@l����.�C:2:��-V�%M�[Խ��dbH���%s>* �V���mv7N�>{4j�}қ���>;
    �F�u-*X�s����aak?�L��׌�L�v�qn.��rɇB�ӻc�:[���ѷk5Z�=(��to�:7�2[}���Q�H�}���	>[jU]�d�X�Mz��4kC�.��$�.�
    ��]r��8�����m��gRB|v���\&U�P���,���%^�L ��v�1�&�f]�nL\D�a�PK��WFA"���!lib_files/Crystek.sfm��iLWpP)4�R*[K�f`vٓ�8�b�
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    рҮZ��AQ�@E!B�x�X�{Û�vf��f��2�����c�����E�[+�3RRca��B��B�8�Kp�.==�K=��K��V���;E��R�ccSS�׫����&z�#yibV�ߵyh�A�ڏ_�_
    �����!í���-�7n��8$+�4�y�Ү&���Et���q ������^����FR����0�"!#�[�:h3=vw7�h:q��Z��e�\c�:8k�V���O#�>�5�adCd:[Է!�#>}��Ft$d��F����2fT�'��6R-RNX�E?�2J���#WF>B�2�9��H��r��5�hU�u���w�Z��o��|c�}�k]��N���2�9��H�(�L�m�e�<R*�]���ѱ�UY7Djǟ;��&$�����H�c|�9��H��}�32����2�<�f}���}���rI�ݑ0�%RƍetHx��+%I��xR���HT9��6���w�呲�-M�*R6��O���B�v��
    ��eR�T��6��@�Vk#�ʣ�!�Qqo�=c=�����zv������������,�ƙyC��E��q�2�X`�	�($�'���}��8XUU�ٹQ�KjI;|]'+m�Ulw!�����w��=�m;GF`dc|s��HȨ���4ZsΦ��\Ӕ��F�f��é���َU������##�;��f0�"!��;'�6/�	̞�'�Q�P����})x�,�`����HmY)����4Q֝.�e\�i$��`�"!�†k�FW��Gsʖ������^&�ߺtmd�2�Ν�������K�QkT$d4���4�/qx��G���C�ڴ�퉊��&���U�;����y8�^�L7�"!��D�?��9�F^d�-Y��R8�慣<r �F�'*?})GF��||̑GT$d�:�~r9��i�#f�+�L���X���q�Ȋ�G9�����DžQ �#�+3�l� 2��}�chs�<k�h?���G��Jf;��p�I����wZ'"k�WӹeF
    ��Ua�@`��a$d��K���[��~}w"�Gd�<Y���-��J��z%GF��?��FT$dT���&9������2�w�5_�F[�����@y��2�!�,\ĕ�X"���&�~�HȈx߭�x�F�7Vk՞�*�h������h���2ѝ�?�P����Wf�Z�"!�ƞu�M]���e�Z�:�6<Y;q�-
    ����&�ٸVpb��|>���<2����_7TA��	'N1��	xú���H����'���5w��A����n�b����ȓz��yd	�?%:�
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    Petre

Reply
  • Hi again,

    I created a configuration in ADIsimCLK that takes an ideal 100MHz clock reference and it passes it through the AD9523-1. I then used the Crystek CVHD-950 of 100MHz. I then set up several 100MHz outputs, each with a different driver: LVPECL, LVDS, CMOS, HSTL. The tool provides the expected phase noise for each of these choices. If you had a phase noise analyzer, we could compare your results against these. 

    I attach the report: 

    AD9523_1_setup.clk analysed at Wed Jan 29 16:31:23 2025 
     
    Clock Chip is AD9523-1 
    VCO is AD9523-1 
    Reference is custom 
     
     
    PLL1 Loop Filter specified by: Phase Margin 
    	Design Objective:  Loop Bandwidth: 30.0 Hz   Phase Margin: 75.0 deg 
    	Simulation Result: Loop Bandwidth: 31.04 Hz   Phase Margin:  82.9 deg 
     
    PLL2 Loop Filter specified by: Phase Margin 
    	Design Objective:  Loop Bandwidth:  450kHz   Phase Margin: 75.0 deg 
    	Simulation Result: Loop Bandwidth: 445.8kHz   Phase Margin:  74.5 deg 
     
    Power Dissipation Estimate 
    Core			 325mW 
    Ref single		4.0mW 
    OUT0			48.6mW 
    OUT1			30.4mW 
    OUT2			35.9mW 
    OUT3			57.8mW 
    OUT4			92.1mW 
    OUT5			92.1mW 
    OUT6			92.1mW 
    OUT7			92.1mW 
    OUT8			92.1mW 
    OUT9			92.1mW 
    OUT10			92.1mW 
    OUT11			92.1mW 
    OUT12			92.1mW 
    OUT13			92.1mW 
    PLL1_OUT		24.4mW 
    Total Power		1.45 W 
     
    OUT0:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      SONET OC-1 Jitter =  110fs rms 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT0 is 0s 
     
    OUT1:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT1 is 0s 
     
    OUT2:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT2 is 0s 
     
    OUT3:  
      Frequency: 100.000MHz 
      Broadband Jitter (>1kHz) =  212fs rms 
        SNR =  77.52dB  ENOB =  12.92bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 98.4fs rms 
        Phase Jitter EVM = 0.0062 %rms 
        Phase Jitter =   0.004 degrees rms 
        ACI / ACR =  -87.2dBc 
      Delay from Ref to OUT3 is 0s 
     
    OUT4:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT4 is 0s 
     
    OUT5:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT5 is 0s 
     
    OUT6:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT6 is 0s 
     
    OUT7:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT7 is 0s 
     
    OUT8:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT8 is 0s 
     
    OUT9:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT9 is 0s 
     
    OUT10:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT10 is 0s 
     
    OUT11:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT11 is 0s 
     
    OUT12:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT12 is 0s 
     
    OUT13:  
      Frequency: 500.000MHz 
      Broadband Jitter (>1kHz) =  218fs rms 
        SNR =  77.28dB  ENOB =  12.88bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 96.2fs rms 
        Phase Jitter EVM =   0.03 %rms 
        Phase Jitter =   0.017 degrees rms 
        ACI / ACR =  -73.4dBc 
      Delay from Ref to OUT13 is 0s 
     
    PLL1_OUT:  
      Frequency: 50.0000MHz 
      Broadband Jitter (>1kHz) =  180fs rms 
        SNR =  78.94dB  ENOB =  13.16bits 
          at IF Freq =  100MHz 
      Integrated Phase Noise from  100kHz to 1.25MHz 
        Timing Jitter = 39.0fs rms 
        Phase Jitter EVM = 0.0012 %rms 
        Phase Jitter = 0.00070 degrees rms 
        ACI / ACR = -101.3dBc 
      Delay from Ref to PLL1_OUT is 0s 
     
    Frequency Domain Analysis of PLL2 
      Analysis at PLL output frequency of 3.00GHz 
     
    Phase Noise Table  
    Freq	Total	VCO	Ref	Chip	Filter 
     100 	-76.92 	-149.1 	-77.61 	-85.25 	-180.2  
    1.00k	-93.45 	-135.1 	-101.3 	-94.23 	-160.2  
    10.0k	-105.8 	-121.3 	-125.4 	-106.0 	-140.4  
     100k	-111.5 	-115.7 	-129.8 	-113.9 	-126.9  
    1.00M	-124.4 	-132.3 	-139.2 	-126.1 	-133.4  
     
           ----    End of Frequency Domain Results   ---- 
     
    Transient Analysis of PLL2 
      Power up transient to frequency of 3.00GHz 
      Simulation run for  349us 
     
    Frequency Locking 
      Time to lock to 1.00kHz is  330us 
      Time to lock to 10.0 Hz is  344us 
     
    Phase Locking (VCO Output Phase) 
      Time to lock to 10.0 deg is  324us 
      Time to lock to 1.00 deg is  330us 
     
    Lock Detect Threshold 
      Lock Detect output did not pass 2.50 V 
     
           ----    End of Time Domain Results   ---- 
     
           ----    Summary of Settings   ---- 
     
     
    Reference	custom 
       Frequency	 100MHz 
       Phase Noise	None 
     
    PLL1	 
       Design Freq	 100MHz 
       VCO	CVHD-950 
          Tuning Law	Datasheet Kv 
             Kv	1.21kHz/V 
             V1	0V 
             F1	99.998MHz 
             V2	3.30 V 
             F2	100.002MHz 
          Input Cap. (Ct)	0F 
          Phase Noise	Table 
             PN Floor	-162 dBc/Hz 
       Dividers	 
          R1	1 
          N1	1 
       Phase Detector	 100MHz 
          Icp	16.0uA 
          V max	3.30V 
          V min	0V 
          ABP Pulse	0s 
          PN Floor	-219dBc/Hz 
       Loop Filter	AD952x LF 
          Specify:	Phase Margin 
          Loop Bandwidth	30.0 Hz 
          Phase Margin	75.0 deg 
          Zero Loc.	3.38 Hz 
          Pole Loc.	 266 Hz 
          Last Pole Loc.	 799 Hz 
          Cpole1	1.50nF 
          Rzero	10.0k 
          Cext	4.70uF 
          Rpole2	 165k 
          Cpole2	 337pF 
          Rext	0 
       FreqDomain 
          Min Freq	1.00 Hz 
          Max Freq	1.00MHz 
          Pts per Decade	10 
          Analysis at	 100MHz 
     
    PLL2 
       PLL Setup 
          Min Freq	3.00GHz 
          Max Freq	3.00GHz 
          PD Freq.	 200MHz 
             Ref Divider	1 
             Ref Doubler	enabled 
          Design Freq	3.00GHz 
       VCO	AD9523-1 
          Tuning Law	Multiband 
          Phase Noise	Table 
             PN Floor	-173 dBc/Hz 
       Chip - PLL	AD9523-1 
          Main Divider 
             Prescaler P	4 
             Min ctgs div.	Not Used 
             Counter Bits	13 
             Min value	1 
             Max Freq.	3.10GHz 
             Max PS Out Freq	Not Used 
             Min Freq.	2.93GHz 
          Ref Divider 
             Counter Bits	10 
             Min value	0.500 
             Max Freq.	 400MHz 
             Min Freq.	0Hz 
          Phase Detector	Charge Pump 
             CP Current	 515uA 
             Polarity	positive 
             Leakage	0A 
             AB Pulse	Not Used 
             Vsupply	3.30 V 
             Vmin	0V 
             Vmax	3.30 V 
             Max Freq.	 250MHz 
             PN Floor	-226 dBc/Hz 
          Lock Detect	None 
       Loop Filter	AD952x LF 
          Specify:	Phase Margin 
          Loop Bandwidth	 450kHz 
          Phase Margin	75.0 deg 
          Zero Loc.	50.7kHz 
          Pole Loc.	4.00MHz 
          Last Pole Loc.	12.0MHz 
          Cpole1	8.00pF 
          Rzero	1.85k 
          Cext	1.80nF 
          Rpole2	 900  
          Cpole2	16.0pF 
          Rext	0 
       TimeDomain 
          Type	Power On 
          Frequency	3.00GHz 
          Stop Time	 349us 
          Max Time Step	 250ps 
          VCO Autocal.	enable 
     
     
     
     
     
    Clock Dist.	 
       VCO Freq	3.00GHz 
       M1 Div Output	1.00GHz 
          M1 Div	3 
       M2 Div Output	1.00GHz 
          M2 Div	3 
       OUT0	OUT0 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT1	OUT1 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVDS 
             Output Current	3.50mA 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT2	OUT2 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	CMOS 
             Max Frequency	 250MHz 
       OUT3	OUT3 
          Frequency	 100MHz 
          Divider	 
             div N	10 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	HSTL 
             Output Current	8.00mA 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT4	OUT4 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT5	OUT5 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT6	OUT6 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT7	OUT7 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT8	OUT8 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT9	OUT9 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT10	OUT10 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT11	OUT11 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT12	OUT12 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       OUT13	OUT13 
          Frequency	 500MHz 
          Divider	 
             div N	2 
             Phase Offset	0 
          Duty Cycle Corr.	Enable 
          Output	LVPECL 
             Voltage Swing	 780mV 
             Termination	Option 1 
             Max Frequency	1.00GHz 
       PLL1_OUT	PLL1_OUT 
          Frequency	50.0MHz 
          Divider	 
             div N	2 
          Output	CMOS 
             Max Frequency	 250MHz 
     
    Timing An.	 
       Start Time	-1.00ns 
       Stop Time	50.0ns 
     
    FreqDomain 
       Min Freq	1.00kHz 
       Max Freq	 100MHz 
       Pts per Decade	10 
       Analysis at	3.00GHz 

    This is the phase noise you should obtain for a LVPECL 100MHz output:

    This is for 100MHz LVDS:

    This is for 100MHz CMOS:

    This is for 100MHz HSTL:

    This will give you the characteristics of your 100MHz outputs.

    I attach the ADIsimCLK file (take out txt extension before loading it).

    AD9523_1_setup.clk.txt

    I also attach the lib files you need to install in this folder (maybe two of them come already installed, just check first). You need to first take out txt extension, then unzip them, then copy the content into this folder: C:\ProgramData\Applied Radio Labs\ADIsimCLK\lib\VCO

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    Y�m�Y ۅYy#���U����A���X��No��ѶE�\����j�+��P;�i��À�[�h7��HԀr������ч��g�c��g�V�U�/K�[C��c<��~��ptB�gw0���3��'B1AV:��������'�hJWDS���.w�_��1�Z�	��C��	�k0��9��n��^���0#	�k�f@�O��e(���>�A�
    ӪzTY�y���M�I�(��g��	�نb�����v�z��7���&�[4��͖��{2ΐ]o��W� (vޙy 'Y�^���	��P#��m��8\���Z����@�]�סL���z tv���@2��n*~�j���[9��>��s��9�oG��Q?B2�9�0 3��
    |�X�t1���;���TG/�p;5a|Sx�@Ng_�q�F<4��0ta�zB2C�*��Y-D�����.���zP�r|�f�f�Nb��B̖���ã��c1..I#�$�1g��^�D���$��~��41��Sh����H�zt���z�7���x��V�7�^��l��^�!���2ҼȍA�ac`�j��LGB%�X4��¨�)$
    ���<��L����������
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    ���+�Е�9�.��'�5�ˣѠ�]�x�U�����]�U��#�z&ë,��:=Vx`i)2�AH!�8
    PGW�+��5H�x�`�x��=�}D�h^=�6�	�:���0&O,i6ϋ�vU�	-(g���b�)������t�Fg]�0������:�݆J��j��B�2�T�Љ�����:Q�1)4YW��b�$��]ŀW�H�X��/N�:� y���M�$�(,�9�QJv�m��*6̌y��zC7�)݀v	ݖn@��y�/!�+�����7L�y�u�YҘ���qh�a��p�k������x&�A�
    �m;�`U?�!ԕ7�e艈1��9�!}h�ИʴÅ-�2̼8)��jQ������	#OG��~��A�I:����r��xW�������l�v��(P���f���A��i�Lh�O+P�,���3~ؖPۊ?gs�����������2�;�6����v�ڜʹ��������\Q�Fcԋv�)M�C=�|)�a�C=p��pE�@�{�a��u)Tw臒5\�6�L������mu��3�b@��T؛~�I�WX��m/�S�	���i����V)DsC�"|\	�d+d�S�VL�|�?qJd�l|�N$	�V�P�Kj���˃h�a�i%�!T�|ȉ:i%E��lP-�+*b�C�F#�{
    ����K�XE��TH�!�H��ׯx�k8rûd�4������2�}D��W��rW��qʝ����ޠ���a^�+h��A2�i��p�@�x?��}dD$6Ar���A3E�CR��T $�\�6M�u�&]�&M�xỜԱ��k��Uɀ�2*�U��!/\T��>^9�`X�̋�2��]�C�d���P���n&M��[B��-����%/�;.�c��?�r�Gl��7��-�0n��%�Ѓ�J0�o#�9x$���0���]����`IPy�W�ZR�YCm犉��|r:���:,W�=�)�02�I�������a[z*Q��x�t@"e��v�t�ZB��+��3zU?���΁��:��
    �%�8k�F�5j!�>�Z����zqj�~�'WґɬF�RåE���2�
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    MC����jfׇm����ذ��0��TS袵��=�bs(�R�����N���E�Ll&)%�SX����Ԇ�)����X\8q
    &p��}M�aMn�d����V��{n'�r������:ꈀ��j��VfOf��\g�_-�����X=y�k�,x�.�#��]�,轖��т�.<a��5(:-�i����GȽ����#�1�Wװ͕�(�`��G5� �.i�Pf��V}5�A��ldC"�ydf�Ѩ��Q�I��|�,}�����̾�U�jYF3U���4q"��zƾz�쫷hq����6(�a���4�����H;Ȣ(�I�ș|�Ț�����V�o��b�B�,?����a$�X��RX�\t�.�Z�	��B|?��dA ����B��6S�Rҁ�y l�Z���v�J���G/�2,�p�iFa����<���+��n�ש��eF�&����i�A��\��R�`�Ah���޳��T�}�ay�3�v:�訲�-�~"�1p�rqJ�ɤ�f.g�9�~�����#����1}/l�l=�r^�F�4��fEV�g�k���!�@*��5 !���z�[�z�� ~3=P2=�c���&��f"�b�8Q3�Πf"B�%�n�M�D�A@�nePQ3,�d5�H�����䕪��$Q�� Ŕ�db��{6b޳��X�"e��Ϲ��"ep�o�q�a�4fY�H�:�#A�5_V�5Y�u3�.����2�,���c[X�PNaWƂ�h<�:K`�O�xl��ũ\���r?i�XZKg��©9�ރgxu\�Le٨˗&�}̾i� i���j��4b
    ����q�����)nZ�Ly2n��{�I����/�>R����X�9��?'i��E+���l�ta"�m3&��t`}�Ue�����` ���E��#h3�3�󰎂w�ZZ�����D]�ɸ)�$W��5�`�aQY���k��*"����lx<���q6�^y"���qA�Ⱦ
    �A���>s�K���qqR�`���l(�k/�H�]<�)��07�@��y׻�vk�*��R�{/��ګ��cE�J�ҧ�J%u����w`.�s��L�1P�)��<5B�4%P6&�00�w�*����C��\�Gڷ���%�nKϜ�I��^I
    ��
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    ��&8��4Jl���d�0�̡�1���%�g��禹'E�5��RU]A��RX�Ϛ]���R;֓u5��)=�n-[a�	$~�k�êe.ɟ�1�E�9@H:�Iex�Ƕ��r�S�C	������÷�^	Pg������۪?:W��x�S&'z���iq
    5��~�B
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    �t�A7���<��*�r�������aYs?�P4��t���W"���*�U[��T/�^]��
    �#�k_�M��'`�r��N�)�b��NlۖY�gAw��8L�lC�i5N�n��M�}��J�L��6���s��v��m��B�vm.�n�Ԧ�n����lӜXu�`���h�LvJ��a_�A'su�}��V����ڦ(3b�>g�feZ�
    	5˼++���I@͌h���tl�q�\?����J墑����rNq���,�D�SG����S��
    �:�}'�Ꮦ��`}�*=�m�5G���j)o���,&��TM2��z�5�5X#hx��p���k���#DԸr����wc�Wgc���O0��Dݸ}���-$�a�k����K����Dc�ۤ-m��oSP7�褪�m_)�[d��6@
    }�&��;Ż���@M�'�ڦ��D\�m�2��ST���NI?A@��奍m�P�z���6����eC\���|0�� ��2S�����E}{F6��˜D	� P���������@������HE]��e̊�|,O��*��"l5n3�S,i4��`�Y{�Twj(�g����ЋO���{��P�)��d���HF1�Pa(��l�xp����0���5�LzFk�U�2�X�l՗������rU6�X��{E//änKFq�6��蘎<�p9�0��;m�@�$3/kt�北��z�A��lBd�d��/��N�k�^T}B/2���9U��D��\�{9�e�Y1�5��b��[�UVn�ٺ�Aׂ��Z�i��4!��
    +��H�\E���c�?	p�}eʰ�E�s/�X�1���ӬZ�9����r�4s�斣��T��C�"J�;ֶ�,Yp�	������:@�oY"��ɠ�(hɦ�Š�̜f���A�}P!9Lٝ:��mj���d��)��<���Q�Q��׻��ʣ��lN�^V',��fD����[s��r���2Ul&@�j~Q*d���>�I�;���0��m�]�֍�M�m�2[jy.�E�q�8K�P����!@�C*0n,J#��/SxUJ�P��!j)�7�쥂M:뾕�p�ͽ�Ѓӻ�a�]qE)tf��R����'l#k�94e7��C)�=.~�
    �-�ǟ%��}N˺tR���h�� =`Z-��2Z�T��Rpdg����r�!L��M�Z�!�֠�s"��?����L����e�Y(�9������/Y�v����)��}�P P7�Ot�O��R��/c����#Ď[��8�#D�[3���j��w�])%�X
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    tK���0W?T��fn�����V*=,o�N⊓�NX�iW�$Ҙ5f�	��/W�������#�Tc*�?/�OF����d��>�S�,�7Ȥ5K��λin���/����~c�S��$'���	N�~�W�����u��@�aNv���v(^9f8*D�iN".VC�\�s���4a	��[��l¢�I%���6A�������i�{/T�	�A>y��%�pk�]�r��QƬ�N�,�^��6V�
    ��4<pW��a��k��J	aH�0e��b�qV0ve��+hJ��v\�̥�EI�pn7��ā�8{ܷ|7���x��"86�H8 Z�H����=��ZI��%DC����ڤ�X�J
    eKϥ[l{"�T��W}��PWV����Ǝ�O�����|�^v����#��Ɏ�3�kT�3|Q����6��	�:R��M���zƒ���u�Uǟ�\GP9$og������"�o����!��#ֱ�mQ&)j7��&;uX50C�Q^G�Ӫ��0EkS+����V:u�.A@�O2�J�n�Ӣ�	t�r��d�Lک����T�5Yí$%�v4-X�t��c*�D'�;�D���d����}p3�WKT��'a�DY]��O)�(j����.�~7��u�=����F�\wR&\����C6�G�<7�Ayj�7����_�$a��y���
    �<�R��]�����L�b�`�(���(�*�ktV�N@wsU�,�M�5�(����5���
    X�	h*��r�']����4y�"!���7��:J���Gy�]!�F����M�-m�(2�.`!<C ȟ���]Ɏ)(m�\<�r��.XZ�ܚ�O1 ����iٴ���%��\Ie�̜]� gB����5Mے��/�v�L��D��i ���XP���U�c�M親191MqZm!��4�GR�@ȴn��DO�ʑRUa�B��L�n���b�ܪ�
    �t�W2�>�����]�'��{�h�[(�(�,�>J'����{�pmS����r�r��e�����n�D��;��n�O��
    ~�0/�����w1*����1Os��f�ف���و^�s)�p%=��[\����b�W�@9�R/n��ѩ;�N�n��^zc�]F�j����,[��|�ml�K#L��n›��6��B3�\��Ο#X^��vY�{2�vn�D������`�.�R\*�@��R[<{\f�.� �8����h$R��nНi&�0sV��Id�qh�3�0�t62,�mpK�}r|�24�����ѓ��hյ3��f�2�}|���D8�R��W��%���/�VX������D����ź�_�^I	t>M3�-_�fF���̲[������^��[��dp-�dVA"+ƣ��l1�Y�
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    �4�[��˕�����2U��(�\�4!���B��i-i�?'��-�aw�y��E��!�N��b���C8"N���Sy%�)�>G���a�3�H�ed����;��%�y�n0|��-��C��<�Q�H�����`%o�.^���g+��|D��h�,g8q"�>l�j��+���ʙ�F�d�>}%P�y��<3�}tq��|��2w�h�
    =���Y'�:��⍙Z��"�����c)`�pY�ZW&β�f<S��?��-1��"�-�&��
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    �F�u-*X�s����aak?�L��׌�L�v�qn.��rɇB�ӻc�:[���ѷk5Z�=(��to�:7�2[}���Q�H�}���	>[jU]�d�X�Mz��4kC�.��$�.�
    ��]r��8�����m��gRB|v���\&U�P���,���%^�L ��v�1�&�f]�nL\D�a�PK��WFA"���!lib_files/Crystek.sfm��iLWpP)4�R*[K�f`vٓ�8�b�
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    �����!í���-�7n��8$+�4�y�Ү&���Et���q ������^����FR����0�"!#�[�:h3=vw7�h:q��Z��e�\c�:8k�V���O#�>�5�adCd:[Է!�#>}��Ft$d��F����2fT�'��6R-RNX�E?�2J���#WF>B�2�9��H��r��5�hU�u���w�Z��o��|c�}�k]��N���2�9��H�(�L�m�e�<R*�]���ѱ�UY7Djǟ;��&$�����H�c|�9��H��}�32����2�<�f}���}���rI�ݑ0�%RƍetHx��+%I��xR���HT9��6���w�呲�-M�*R6��O���B�v��
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    ��Ua�@`��a$d��K���[��~}w"�Gd�<Y���-��J��z%GF��?��FT$dT���&9������2�w�5_�F[�����@y��2�!�,\ĕ�X"���&�~�HȈx߭�x�F�7Vk՞�*�h������h���2ѝ�?�P����Wf�Z�"!�ƞu�M]���e�Z�:�6<Y;q�-
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    ه��g�d��I/��B<��Q{HG�\�8S��>�47y�m	�����G[�Ul#؏�oͤ���+J[纍z���i���+����/5GQ���*���o�dt�W|�L���u/�qo��w�G�`0�D�BL}�7����'�A���:���ʦ
    t�%�a7x�e9��Xy$��N��2X|���"Q=��J2�4e�F��2�j�G��}G��@�6��G����y�v����H��<������F��G�C{�_��*ʨey�^Ǭ��<"��}�##[V�ez�lj
    92���c3Q����V�C�>{wŏ#1ܟ֯��n��~9)�~O������I�'E���t#*2?o�F��vt3�βˤ�z��n�Gy�Ϊ���Xm����PK�dM?���WIlib_files/CrystekVCXO.libݐ_O�0�ߛ�;��	lݰ�	���,�!J6�L�h�ز�@����"Q�|�/=�����7\I8�Xe5��)-aV��I8d`z²��j�XÙ8���ඪ��9<�\��q�Cܢ̥�N����n�8d�W�1���Z.�Q��&�n��h+�(��2��\~+ڍ��4y�5��f!���Į�s�*��U���0:B���21!��D�w���$|�F�Fk����q�3m^��م����(�ՌYݚKj����!�t�K9�� �״k|V8dZ���03�ߙ�k�ƕ�����+B�/h)b�:�4��-���EN��Z��'r�w�PK��WF�O���lib_files/CrystekVCXO.sfmcb```eH```w.�,.I��p�pѵ45�///�K��%���"��TbN1H\��/.HM�-�HM-)�/K��ׇ��W������z�#�N=;L�@p9��x��o�������g��~�\���}��&F�r}�#�����J�`�!,~
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