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High spurious at output frequencies

Category: Software
Product Number: AD9523-1

Hello,

I configured one of AD9523-1's output as LVDS 7mA type. and when I observe the output at spectrum analyzer I'm getting high spurious. for your reference I'm attaching the screenshorts and the configuration file. please, tell me why am I getting like that. and how to resolve this.

"AD9523 Regmap File"
"Rev.","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","10000001","81"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","00101000","28"
"0011","00000000","00"
"0012","00000100","04"
"0013","00000000","00"
"0014","00000001","01"
"0015","00000000","00"
"0016","00101000","28"
"0017","00000000","00"
"0018","00001100","0C"
"0019","00011111","1F"
"001A","00011010","1A"
"001B","00010111","17"
"001C","10010000","90"
"001D","00000000","00"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","00000111","07"
"00F1","10000111","87"
"00F2","00010011","13"
"00F3","00000010","02"
"00F4","01000000","40"
"00F5","00000000","00"
"00F6","00000000","00"
"00F7","00000001","01"
"00F8","00000000","00"
"00F9","00000000","00"
"00FA","00000000","00"
"0190","01110011","73"
"0191","00001001","09"
"0192","00000100","04"
"0193","00100000","20"
"0194","00011111","1F"
"0195","00000100","04"
"0196","01101000","68"
"0197","01100011","63"
"0198","00000000","00"
"0199","01001001","49"
"019A","00001001","09"
"019B","00000000","00"
"019C","01001001","49"
"019D","00001001","09"
"019E","00000000","00"
"019F","01001001","49"
"01A0","00001001","09"
"01A1","00000000","00"
"01A2","01001001","49"
"01A3","00001001","09"
"01A4","00000100","04"
"01A5","01001001","49"
"01A6","01100011","63"
"01A7","00000000","00"
"01A8","01001001","49"
"01A9","01100011","63"
"01AA","00000000","00"
"01AB","01001001","49"
"01AC","01100011","63"
"01AD","00000000","00"
"01AE","01001001","49"
"01AF","01100011","63"
"01B0","00000000","00"
"01B1","01001001","49"
"01B2","01100011","63"
"01B3","00000000","00"
"01B4","01101000","68"
"01B5","00001001","09"
"01B6","00000100","04"
"01B7","01010011","53"
"01B8","00001001","09"
"01B9","00000000","00"
"01BA","00000000","00"
"01BB","00000000","00"
"022C","00000000","00"
"022D","00000000","00"
"022E","00000000","00"
"022F","00000000","00"
"0230","00000000","00"
"0231","00000001","01"
"0232","00001101","0D"
"0233","00000000","00"
"0234","00000001","01"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00101011","2B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000011","03"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"

  • ADI North America will be on winter shutdown starting December 24, 2024; perhaps another community member can assist you until our return on January 2, 2025.
  • I compared the schematics of our board and AD9523-1 Evaluation board. we made changes in our as mentioned in the schematic. spurious got reduced, but not completely. would you please suggest me the values of C5, R5 for external loop filter capacitance.
    Here, I attached the pll1,pll2 controls also. kindly suggest me weather the configuration I provided is OK or do I need to modify at any where.

  • Hi,

    you sent some signal analyzer spectra that say the carrier is 100MHz. You also sent a register map file that does not have the reference clock frequencies. I therefore suppose you have a VCXO=100MHz and REFA=100MHz. If this is true, then:

    - this is the PLL1 configuration I propose: REFA divider=1, PLL1 feedback divider=1. Anti backlash pulse set to minimum because only in this way the PFD frequency may be 100MHz. Again, not clear what REFA or REFB clocks you use.. 

    I changed the PLL2 by increasing the PLL2 charge pump current to the max. As a rule: you want PLL2 working at the highest loop bandwidth and therefore the charge pump current should be close to max. Start with max value and then you can reduce it a little to modify the phase noise profile. You should use a phase noise analyzer, not a signal analyzer.

    I attach the stp file I created. I did not test it on an eval board, but it should work

    Could you please send me the schematic that you used in your tests?

    Petre

    ;Header contains information about the setup file and revision
    <Header>
         Product = AD9523-1
         FileVersion = 1.0
         DecimalSeparator=.    ;Used for internationalization
    </Header>
    
    <RegisterMap>
         &h0,&b10000001   ;81 Hex, 129 Dec
         &h2,&b00000000   ;00 Hex, 000 Dec
         &h3,&b00000000   ;00 Hex, 000 Dec
         &h4,&b00000000   ;00 Hex, 000 Dec
         &h5,&b00000000   ;00 Hex, 000 Dec
         &h6,&b00000000   ;00 Hex, 000 Dec
         &h10,&b00000001   ;01 Hex, 001 Dec
         &h11,&b00000000   ;00 Hex, 000 Dec
         &h12,&b00000001   ;01 Hex, 001 Dec
         &h13,&b00000000   ;00 Hex, 000 Dec
         &h14,&b00000001   ;01 Hex, 001 Dec
         &h15,&b00000000   ;00 Hex, 000 Dec
         &h16,&b00000001   ;01 Hex, 001 Dec
         &h17,&b00000000   ;00 Hex, 000 Dec
         &h18,&b00001100   ;0C Hex, 012 Dec
         &h19,&b00010011   ;13 Hex, 019 Dec
         &h1A,&b00011010   ;1A Hex, 026 Dec
         &h1B,&b00010111   ;17 Hex, 023 Dec
         &h1C,&b10010000   ;90 Hex, 144 Dec
         &h1D,&b00000000   ;00 Hex, 000 Dec
         &h1E,&b00000000   ;00 Hex, 000 Dec
         &h1F,&b00000000   ;00 Hex, 000 Dec
         &h20,&b00000000   ;00 Hex, 000 Dec
         &hF0,&b11111111   ;FF Hex, 255 Dec
         &hF1,&b10000111   ;87 Hex, 135 Dec
         &hF2,&b00010011   ;13 Hex, 019 Dec
         &hF3,&b00000010   ;02 Hex, 002 Dec
         &hF4,&b01000000   ;40 Hex, 064 Dec
         &hF5,&b00000000   ;00 Hex, 000 Dec
         &hF6,&b00000000   ;00 Hex, 000 Dec
         &hF7,&b00000001   ;01 Hex, 001 Dec
         &hF8,&b00000000   ;00 Hex, 000 Dec
         &hF9,&b00000000   ;00 Hex, 000 Dec
         &hFA,&b00000000   ;00 Hex, 000 Dec
         &h190,&b01110011   ;73 Hex, 115 Dec
         &h191,&b00001001   ;09 Hex, 009 Dec
         &h192,&b00000100   ;04 Hex, 004 Dec
         &h193,&b00100000   ;20 Hex, 032 Dec
         &h194,&b00011111   ;1F Hex, 031 Dec
         &h195,&b00000100   ;04 Hex, 004 Dec
         &h196,&b01101000   ;68 Hex, 104 Dec
         &h197,&b01100011   ;63 Hex, 099 Dec
         &h198,&b00000000   ;00 Hex, 000 Dec
         &h199,&b01001001   ;49 Hex, 073 Dec
         &h19A,&b00001001   ;09 Hex, 009 Dec
         &h19B,&b00000000   ;00 Hex, 000 Dec
         &h19C,&b01001001   ;49 Hex, 073 Dec
         &h19D,&b00001001   ;09 Hex, 009 Dec
         &h19E,&b00000000   ;00 Hex, 000 Dec
         &h19F,&b01001001   ;49 Hex, 073 Dec
         &h1A0,&b00001001   ;09 Hex, 009 Dec
         &h1A1,&b00000000   ;00 Hex, 000 Dec
         &h1A2,&b01001001   ;49 Hex, 073 Dec
         &h1A3,&b00001001   ;09 Hex, 009 Dec
         &h1A4,&b00000100   ;04 Hex, 004 Dec
         &h1A5,&b01001001   ;49 Hex, 073 Dec
         &h1A6,&b01100011   ;63 Hex, 099 Dec
         &h1A7,&b00000000   ;00 Hex, 000 Dec
         &h1A8,&b01001001   ;49 Hex, 073 Dec
         &h1A9,&b01100011   ;63 Hex, 099 Dec
         &h1AA,&b00000000   ;00 Hex, 000 Dec
         &h1AB,&b01001001   ;49 Hex, 073 Dec
         &h1AC,&b01100011   ;63 Hex, 099 Dec
         &h1AD,&b00000000   ;00 Hex, 000 Dec
         &h1AE,&b01001001   ;49 Hex, 073 Dec
         &h1AF,&b01100011   ;63 Hex, 099 Dec
         &h1B0,&b00000000   ;00 Hex, 000 Dec
         &h1B1,&b01001001   ;49 Hex, 073 Dec
         &h1B2,&b01100011   ;63 Hex, 099 Dec
         &h1B3,&b00000000   ;00 Hex, 000 Dec
         &h1B4,&b01101000   ;68 Hex, 104 Dec
         &h1B5,&b00001001   ;09 Hex, 009 Dec
         &h1B6,&b00000100   ;04 Hex, 004 Dec
         &h1B7,&b01010011   ;53 Hex, 083 Dec
         &h1B8,&b00001001   ;09 Hex, 009 Dec
         &h1B9,&b00000000   ;00 Hex, 000 Dec
         &h1BA,&b00000000   ;00 Hex, 000 Dec
         &h1BB,&b00000000   ;00 Hex, 000 Dec
         &h22C,&b00000000   ;00 Hex, 000 Dec
         &h22D,&b00000000   ;00 Hex, 000 Dec
         &h22E,&b00000000   ;00 Hex, 000 Dec
         &h22F,&b00000000   ;00 Hex, 000 Dec
         &h230,&b00000000   ;00 Hex, 000 Dec
         &h231,&b00000001   ;01 Hex, 001 Dec
         &h232,&b00001101   ;0D Hex, 013 Dec
         &h233,&b00000000   ;00 Hex, 000 Dec
         &h234,&b00000001   ;01 Hex, 001 Dec
         &hA00,&b00000000   ;00 Hex, 000 Dec
         &hA01,&b00000000   ;00 Hex, 000 Dec
         &hA02,&b00000000   ;00 Hex, 000 Dec
         &hA03,&b00000010   ;02 Hex, 002 Dec
         &hA04,&b00000000   ;00 Hex, 000 Dec
         &hA05,&b00000100   ;04 Hex, 004 Dec
         &hA06,&b00001110   ;0E Hex, 014 Dec
         &hA07,&b00000000   ;00 Hex, 000 Dec
         &hA08,&b00010000   ;10 Hex, 016 Dec
         &hA09,&b00001110   ;0E Hex, 014 Dec
         &hA0A,&b00000000   ;00 Hex, 000 Dec
         &hA0B,&b11110000   ;F0 Hex, 240 Dec
         &hA0C,&b00101011   ;2B Hex, 043 Dec
         &hA0D,&b00000001   ;01 Hex, 001 Dec
         &hA0E,&b10010000   ;90 Hex, 144 Dec
         &hA0F,&b00000001   ;01 Hex, 001 Dec
         &hA10,&b00000001   ;01 Hex, 001 Dec
         &hA11,&b11100000   ;E0 Hex, 224 Dec
         &hA12,&b00000011   ;03 Hex, 003 Dec
         &hA13,&b00000010   ;02 Hex, 002 Dec
         &hA14,&b00110000   ;30 Hex, 048 Dec
         &hA15,&b10000000   ;80 Hex, 128 Dec
         &hA16,&b11111111   ;FF Hex, 255 Dec
         &hB00,&b00000000   ;00 Hex, 000 Dec
         &hB01,&b00000000   ;00 Hex, 000 Dec
         &hB02,&b00000000   ;00 Hex, 000 Dec
         &hB03,&b00000000   ;00 Hex, 000 Dec
    </RegisterMap>
    
    <PinStates>
         PortA=&h1E ;Bit0=USBStatus, Bit1=CSB, Bit2=ResetB, Bit3=SyncB, Bit4=PDB, Bit5=RefSel
    </PinStates>
    
    <SoftwareSettings>
         AutoSendUpdate=1              ;AutoIOUpdate Setting
         REF_A = 100.0000
         REF_B = 100.0000
         REF_TEST = 10.0000
         VCXO = 100.0000
    </SoftwareSettings>
    

  • Hello petre,

        Here I'm attaching the schematic what we used, c62,c58,r39,r41,r45,c62 ,r46 are DNI. I'm using REF B as 10MHz and REF A as 100MHz. once, I'll try with your configuration file by modifying REF A, REF B divider and let u know.
       
        I observed the output of some other clock there I didn't find any spurious in the spectrum analyzer. that's why I used spectrum analyzer to measure the output power.

  • I tried with your configuration, I modified at input ref A, Ref B divider as they were 100,10 MHz. I kept ref A divider to 40 and ref B divider to 4, I E2 as a response from 0x22C register.

  • HI,

    this shows the signal generator you use to provide REFA or REFB clocks is not good. When PLL1 PFD sees a lower frequency, it can lock PLL1. What signal generator you use?

    I do not believe the spurs are created  by PLL1. Did you increase the PLL2 charge pump current? 

    Petre

  • Hello ,

    sorry, yesterday I forgot to modify at PLL1 feedback divider, that's why response was 'E2'. Now, I made modification there and both the PLLs got locked('EB').

    from your suggestion I kept charge pump current to maximum i.e. 892.5uA. and the output is as follows

    from initial to now spurious got reduced. but, still noise floor got lifted and also spurious is there. how can I reduce these?

  • Hi,

    the data sheet gives this phase noise plot for 122.88MHz, a close frequency to your 100MHz:

    In your case, the doubler cannot be used because PLL2 does not seem to accept a feedback divider of 15. This impacts a little the phase noise.

    In your photo, the spurs are at 512kHz, which are close to the PLL2 knee on the data sheet plot. You now have the charge pump current at max (892.5uA) . Start reducing it (but don't go below 850 uA) and see if something happens to those spurs. 

    The anti-backlash pulse is set to min, which the data sheet says it can work with PFD frequencies below 259MHz. See if setting it to low or max, makes any improvement. They work with max frequencies above 100MHz

    Petre

  • Hello Petre,

        I kept charge pump current at 892.5uA and tried changing Anti BL from low to max. in low condition spurious is at 513KHz, in MAX condition spurious is at 511kHz. here, I'm attaching the images for your reference. Is there any setting to reduce the spurious power?



    previously, I shared you the schematic, is that OK or do I need to make any modifications. I have doubt at 11th pin(i.e. LF2_EXT_CAP).


    Actually, we are providing this clock as the reference to the synthesizer(lmx2595). the synthesizer output was not as expected. I'm programming it to 5GHz there the spurious is very high and the output is also not at 5GHz. for your reference I'm providing that image also.

    Overall, we need to get nice output at here.

  • HI,

    I understand that the anti backlash pulse changes did not affect the spur. Please play with the PLL2 charging pump current as well.

    My recommendation is to first determine what phase noise the LMX2595 requires at the reference clock and understand if the AD9523-1 performance is sufficient. 

    I see the LMX2595 accepts inputs up to 1400MHz. Set the OUT13 distribution divider to lower values to create higher frequency clocks at the LMX2595. Adjust the LMX2595 configuration accordingly. See what happens to the spurs at the 5GHz output.

    Try providing the same clocks from a signal generator directly to the LMX2595. See what spurs you get there.

    Regarding the LF2_EXT_CAP schematic:

    The eval board has this schematic:

    It seems you populate R3 and C16, while on the eval board, these elements are not installed. Take them out. Then, R44 is connected at pin 12 of the AD9523-1. On the eval board, the corresponding R4 is connected at pin 14. So you can populate R46 and take out R44.

    Petre