AD9082
Recommended for New Designs
The AD9082 mixed signal front-end (MxFE®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC...
Datasheet
AD9082 on Analog.com
HMC7044
Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
Datasheet
HMC7044 on Analog.com
Hello
We are using the AD9082 along with the ZCU102 evaluation board, based on the reference project provided by Analog Devices on GitHub (No-OS). we are using using AD9082 with a sampling rate 1550msps and clock rate of 387.5MHz . The HMC7044 is used to generate the clocks, and the internal PLL of the AD9082 is being utilized. The device has been functioning properly for the past month, and we have not encountered any issues during that period.
However, recently, we have started facing clock-related problems. Specifically, the Integrated Logic Analyzer (ILA) in Vivado, which is attached to the ADC and DAC clocks, is not displaying any data as the clocks seem to stop. During some power-on sequences, the ADC and DAC outputs are all zeros. At times, the DAC works, but the ADC clock fails to come up. We are experiencing a variety of combinations of this issue intermittently.
We are not using any external off-chip filters in the AD9082 clock path. The user guide for the AD9082 does mention the use of a filter in the clock path. We are concerned whether not using this filter could be causing the ADC and DAC clocks to not free run, leading to the issues we are observing.
Could you please provide guidance on how to resolve this problem?
Best regards
JAlipio - Moved from High-Speed ADCs to Mixed-Signal Front Ends (MxFE). Post date updated from Friday, December 20, 2024 11:16 AM UTC to Monday, December 23, 2024 3:34 AM UTC to reflect the move.
JAlipio - Moved from High-Speed ADCs to Mixed-Signal Front Ends (MxFE). Post date updated from Monday, December 23, 2024 3:34 AM UTC to Monday, December 23, 2024 3:35 AM UTC to reflect the move.
UVLSIDRIVER - Moved from Mixed-Signal Front Ends (MxFE) to Clock and Timing. Post date updated from Friday, December 20, 2024 11:16 AM UTC to Monday, April 21, 2025 9:56 AM UTC to reflect the move.
UVLSIDRIVER - Moved from Mixed-Signal Front Ends (MxFE) to Clock and Timing. Post date updated from Monday, April 21, 2025 9:57 AM UTC to Monday, April 21, 2025 9:57 AM UTC to reflect the move.
UVLSIDRIVER - Moved from Mixed-Signal Front Ends (MxFE) to Clock and Timing. Post date updated from Friday, December 20, 2024 11:16 AM UTC to Monday, April 21, 2025 9:57 AM UTC to reflect the move.
Hi UVLSIDRIVER
Thanks for using AD9082.
I move this thread to the proper forum. Someone here can assist you in your query.
Hello,
Thank you for looking into this query. Kindly connect with the appropriate person, as we are currently at an impasse. Your assistance is greatly appreciated.
Best regards
I wonder how it ever worked without external off-chip filter if you use internal PLL multiplier since off-chip filter is reuqired as stated in the user guide. Could you modify your software/hardware to bypass internal PLL and use external clock to feed DACCLK and ADCCLK? That'd confirm whether issue is related to interal PLL, and you will have to modify the hardware if that's the case.
Hello,
we will try external clock and come back with update.
Best regards
Hello,
Currently, we have not tested the system with an external clock. We plan to focus on debugging the clock path. Regarding the issue of the DAC and ADC outputting zeroes, we've identified that the AD9082 PLL sometimes fails to lock, preventing the AD9082 initialization from completing successfully..We observe that clock that is given as device clock for ad9082 when we read the frequency we should ideally get 387.5mhz but in some cases we are getting 1664khz due to which our PLL is not getting locked. Why does HMC7044 is producing different clock than specified in some power ons.
I think due to irregular clock out from HMC7044 we are facing the issue. How can we fix this?
We are using the project extracted from GitHub.Our configuration is sampling rate is 1500msps and clock is 387.5Mhz for both adc and dac.
Best regards,
Hello,
Could you please provide an update on this? We are currently at a standstill and unable to proceed without resolving this issue.
Best regards
It sounds like the issue is with HMC7044 rather than AD9082 if the reference clock from HMC7044 to AD9082 is not stable. Could you confirm it by reading the lock status of PLL1 and PLL2 of HMC7044 when the reference clock is unstable?
Thank you for providing the details.
We are reading the 0x007D register in the HMC7044 to check the lock detection status. We observe that PLL2 lock detection is reported as 1, but both PLL1 and PLL2 lock detection bit (bit 3) are 0.
Regarding the initialization failure, we are facing two types of issues:
I am attaching prints for both scenarios. Please go through them and suggest a solution.
Best regards.
Thank you for sharing the data. There seem to be multiple issues. Firstly, the behaviour of the AD9082 chip without external off-chip filter is unpredictable if internal PLL multiplier is used. And it appears that HMC7044 also has an issue. I suppose these results are from your custom hardware, and would it be possible for you to try with ADI reference evaluation board?
Hello,
The results are from the AD9082 evaluation board only, not from a custom board. Please advise on how to resolve the issue.
Best regards