LTC6990
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The LTC6990 is a precision silicon oscillator with a programmable frequency range of 488Hz to 2MHz. It can be used as a fixed-frequency or voltage-controlled...
Datasheet
LTC6990 on Analog.com
LTspice
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LTspice® is a powerful, fast, and free SPICE simulator software, schematic capture and waveform viewer with enhancements and models for improving the simulation...
LTspice on Analog.com
I'm using the LTC6990 as a VCO in a PLL. I'd simulated with its model in the past with no issues, but now the output frequency is incorrect for a given control voltage. The problem seems to be that the tool doesn't understand KCL. Since the oscillator frequency is controlled by the current out of the "SET" pin (which is internally regulated to 1.0 V +/- 30 mV), I figured I'd just check the current there in the tool and compare that to what I'd expect it to be. I got about 17 uA, which isn't anywhere near what it should have been. What the current drawn from the SET pin should be can be easily calculated using KCL. Please refer to the image below. (The loop has been broken and I have applied +2.5 VDC to the control input, expecting to get about 294 kHz out, but actually got about 420 kHz.)
VSET is about 1 V, as it should be. The voltage at the op amp output, on the other side of R6 (374 kohms), is about 0.5 V, so the current flowing back through R6 should be (1.0 V - 0.5 V)/374k, which is about 1.34 uA. The current flowing down through R7 should be (1 V)/96.2k, which is about 10.4 uA. The current out of the SET pin should therefore be about 11.7 uA. Measuring the current directly at the SET pin using the meter in the tool I get about 17 uA. Is KCL no longer valid? I cannot use this for any further simulations if the tool cannot calculate currents correctly. I know the LTC6990 model only cares about what it thinks the current at the SET pin is, and that clearly is not correct. Do you have any suggestions as to how i can deal with this?
Thank you.
Hi Barry,
There is already a feedback loop inside the LTC6990 to control the internal VCO mode. The voltage forced on the SET pin is 1V for LTC6993 and it is bandgap-based.
We recommend the circuit below to create a linear VTune-type behavior. Calculations are given on page 16 of the datasheet.
In your simulation, opamp feedback is before the R_VCO. I recommend creating a VCTRL system separately after calculating the needed R_VCO and V_CTRL range.
After calculating R_VCO and KVCO, the rest is active loop filter design. You can follow the loop filter design steps to create an active loop filter.
As a side note, we recommend higher values for DIV resistors. You can multiply your resistor values for the DIV network by 1000.
Thanks
Emrecan
Yes, I'm familiar with the internal feedback loop. The circuit you posted produces an inverting tuning characteristic. I need a non-inverting characteristic. The circuit I'm using is recommended in the data sheet, and, in fact, the inverting stage on the input inverts the inherent inverting characteristic, which is what I need. The circuit in the data sheet that I'm using is quite clever, and I have respect for whoever came up with it. It has worked well in the past in simulations, so I don't know why it's not working properly now. I've worked out the math and the equation shown in the data sheet for this circuit is correct. and the circuit makes sense.
...
If there's something wrong with this circuit, why is it recommended in the data sheet? I've tried placing a simple resistor between VSET and 0 V (GND) and the simulation works quite closely to what would be expected. It's the same as what you have with Vctrl = 0 V. I'd really like to know what changed between my earlier simulations that worked and what I'm seeing now (I know now -- see below).
The DIV resistor values are taken directly from Table 1 in the data sheet, which also stipulates that the Thevenin equivalent resistance of the DIV voltage divider be less than 500 kohms.
Scaling the resistor values up by a factor of 1000 would make the Thevenin equivalent resistance = 923 ohms -- nowhere near the 500 kohm limit, but closer to it than it is now
I even tried placing an ideal voltage source of the correct value directly on the DIV pin and the circuit still did not function properly, so I ruled out Vdiv as a reason as to why the output frequency was wrong. I believe the problem is that the tool thinks the SET current is 17 uA, when, in fact, it should be about 11 uA. The problem exists no matter what voltage is applied to the inverter input.
Now that I've written all of this, in what amounted to essentially sheer desperation, I measured the input bias current of the LT6236, and got about 5 uA, which I consider to be very large (nearly unacceptable in light of the technology available today -- I used to work for a semiconductor company). In earlier simulations I used ideal op-amp models I made from VCVSs, which have identically zero input bias current. I'm not sure why I replaced the ideal models with the LT6236. but I now know for sure I will not be using any LT6236s in a real design. This large input bias current on the inverting input also produces a significant DC error in the op-amp output voltage. Anyway, the 5 uA on the non-inverting input makes up most of the difference in the SET current, so I guess that explains most everything.
Hi,
To control the inverted Vtune behavior with PLL, you have two options.
The first option, you use a positive polarity PFD and non-inverting loop filter.
The second option, you use a negative polarity PFD and inverting loop filter.
About the DIV resistor, I saw that you have used 979 Ohm and 102Ohm. The datasheet states that it should be 976kOhm and 102kOhm. There is another explanation in the below section of this table.
Thanks for your input. There is an online beta tool that you can create an LTSpice file with the desired configuration. Can this configuration provide you with more insight? As you can see in the below diagram, the feedback loop to Opamp is before the R_CTRL resistor.
LTC6990 Voltage Controlled Silicon Oscillator
Thanks,
Emrecan
