CMOS OUTPUT sync of HMC7043

Hi

When output buffers are configured in CMOS mode and phase alignment is required among the outputs, additional multislip delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value of the delay must be as large as half of the selected divider ratio. Note that this requirement of having additional multislip delays is not needed when the channels are used in LVPECL, CML, or LVDS mode.

You can enable the slip and provide a slip value half of the divider value. After you send the reseed request, output channels should be aligned. 

You can reserve the digital and analog delay fine-tuning the output delay more precisely for your system-level requirements.

Please note that the 200MHz input frequency is specified when outputs are in the fundamental mode. Fundamental mode is either the divider value is 1 or the divider is bypassed. If divider value is larger than 1 and synchronization is needed, the minimum input frequency is limited to 500MHz. 

Thanks,
Emrecan 

Thank you for your answer.

I will try to follow this content. If it doesn't work, I will post it here again.

Hi emrecangidik-san.

I understood that multi-slip occurs when using CMOS.

I'm sorry, but plese tell me two things.

　・Why is Multislip required in CMOS while Multislip is not required in LVPECL, CML, or LVDS mode?

　・How much difference is there between individual devices in terms of this amount of delay that occurs in CMOS?

Best regeds.

Channel 0, Channel 3, Channel 5, Channel 6, Channel 9, Channel 10, and Channel 13 generate output clocks that are 180 degrees shifted compared to other channel outputs. This results from the internal structure of the HMC7044/3.  It only occurs in CMOS mode due to the internal structure of the design.

the difference is fixed. The phase difference is 180 degrees. There is no part-2-part variance. 

Thanks,

Emrecan

Channel 0, Channel 3, Channel 5, Channel 6, Channel 9, Channel 10, and Channel 13 generate output clocks that are 180 degrees shifted compared to other channel outputs. This results from the internal structure of the HMC7044/3.  It only occurs in CMOS mode due to the internal structure of the design.

the difference is fixed. The phase difference is 180 degrees. There is no part-2-part variance. 

Thanks,

Emrecan