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how to use the AD9510's distribution section

Category: Hardware
Product Number: AD9510

I want to use the chip's distribution section, input clock is 100MHz from an oscillator, all outputs are enabled, datasheet says i can power down the PLL section to use distribution section separately, but i don't see how to power down the PLL section in register map, could you kindly tell me how to config the register? 

also, in default mode(just enabled all the outputs), the output waveform of out5 is not as same in the datasheet, below is my schematic, out5 is coupled input of clk in AD9268

  

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  • HI,

    to power down the PLL, use bits 1:0 in register 0x0A. Use asynchronous power down because this is what the data sheet uses when it talks about the entire chip being powered down at page 38

    You say OUT5 is used to clock the AD9268. The schematic you show has the OUT5 outputs labelled as CLKBUF0_OUT5_P/N, while the clock inputs of the AD9268 has CLK+/- labels. This tells me that probably there are some other circuits in between. Please show me exactly the schematic between OUT5 and AD9268. It should be a LVDS connection like this:

    I do not know the AD9268, so make sure it can receive LVDS clocks. There are some AC coupling capacitors at CLK inputs, so make sure the AD9268 can introduce its own common mode voltage and the LVDS 350 mV output swing across the 100 ohm resistor is what the AD9268 accepts.

    On the oscilloscope, you should also sense the CLK1 at the AD9510 pins, so you can compare what the AD9510 receives to what the AD9510 outputs. It seems the input clock has some kind of modulation. What clock source you use for this input?

    Petre

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  • HI,

    to power down the PLL, use bits 1:0 in register 0x0A. Use asynchronous power down because this is what the data sheet uses when it talks about the entire chip being powered down at page 38

    You say OUT5 is used to clock the AD9268. The schematic you show has the OUT5 outputs labelled as CLKBUF0_OUT5_P/N, while the clock inputs of the AD9268 has CLK+/- labels. This tells me that probably there are some other circuits in between. Please show me exactly the schematic between OUT5 and AD9268. It should be a LVDS connection like this:

    I do not know the AD9268, so make sure it can receive LVDS clocks. There are some AC coupling capacitors at CLK inputs, so make sure the AD9268 can introduce its own common mode voltage and the LVDS 350 mV output swing across the 100 ohm resistor is what the AD9268 accepts.

    On the oscilloscope, you should also sense the CLK1 at the AD9510 pins, so you can compare what the AD9510 receives to what the AD9510 outputs. It seems the input clock has some kind of modulation. What clock source you use for this input?

    Petre

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