Continuation of ADCLK944: 3.3V CMOS input

Question

Hello. 
 
 In an old discussion about using 3.3V CMOS oscillator as the source for the ADCLK944 as seen below, it was suggested to add a Pullup Resistor to complimentary input just in case you need a bias that higher than VREF.

1) Can you please explain how a pullup would override the VREF connection when the VREF connection is shorted directly to the complimentary input? Did you mean to say you need an additional zero ohm to open the connection 
 and add optional voltage divider to the complimentary input? 
 Im looking for some clarification on this. 
 
 2) Is there any negative impact on the Additive Phase Noise by using an Capacitive divider to the input of this device? 
 
 Thanks

pminc48 · Accepted Answer

Hi 
 I found that EZ enquiry you quote. That knowledge does not exist anymore. 
 I see in the data sheet at page 9 that 3.3V CMOS clocks single ended clocks, DC coupled are accepted. Then it says that the peak to peak differential input voltage swing must remain within 3.4Vp-p. So the negative input should simply be put to ground through a capacitor. The problem I see with this approach is the 100ohm termination resistors that in my view would constitute a load on the CMOS clock and downgrade it. 
 So I would be more comfortable with an AC approach, like the one shown in figure 21. 
 Petre)

pminc48 · Answer

Hi, 
 The data sheet gives an additive time jitter specification that was given for VID=1.6Vp-p, 8V/ns slew rate and VICM=2V. 
 VID is the input differential voltage and VICM is the input common mode voltage. 
 If you apply a 3.3V CMOS clock into a schematic like in Figure 21, the input voltage on the CLK pin decoupling capacitor will be 3.3V p-p, while the clock voltage on CLKB pin will be VREF=2.15V. So VID will be somewhat lower than 1.6Vp-p, which may downgrade somewhat the additive phase noise (basically adding more). 
 My prediction is that the phase noise would not be degraded too much by using CMOS CLK input. I'll see if I'll be able to replicate the test used in Figure 10. That should give you a palpable result. I'll do it for 100MHz (usually CMOS clocks are below 250MHz). I'll keep you posted when I'll have some results. I have to hack an evaluation board first. 
 Petre

pminc48 · Answer

I forgot. I'll do it next week 
 Petre

pminc48 · Answer

HI, 
 
 In the attached, you can find details about my tests today with 1.8V CMOS and 3.3V CMOS input clocks, both of them being ac coupled. 
 When the input is 3.3V CMOS, the phase noise is lower, although at lower frequencies, the spurs are greater. 
 Because the phase noise analyzer accepts only ac coupled clocks, I could not measure the phase noise of the CMOS clocks, so I could not determine the origin of the low frequency spurs. 
 The rms jitter between 12 kHz and 20 MHz is lower as well for 3.3V CMOS clock input. 
 Petre 
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Continuation of ADCLK944: 3.3V CMOS input