AD9546 - Understandind 1PPS behaviour

HI,

we recommend to use the 52 MHz crystal resonator to create the system clock. This ensures the phase noise of the outputs is the best.

We then recommend using the 25MHz OCXO at one of the reference clock inputs (ac coupled for these) or at Mx pins (in CMOS format depending on VDDIOA level) and then use it as a reference to the auxiliary DPLL to compensate the influence of the system clock wonder created by the crystal at DPLL0, DPLL1, AuxNCO0/1, TDCs.

Do you use your own board? I recommend using first the evaluation board, get the configuration tested on it and then transferring everything on a board designed by yourself.

Please send me the stp file you created when using the eval software to create the desired configuration. You should set the DPLLs locking onto 1Hz reference in internal zero delay mode. I remember the chip uses the low to high edge to align the clocks. You may have set the DPLLs in phase buildout mode. The figure below shows the OUT0AP and OUT1AP (1Hz, bottom signals) locked in internal zero delay to 1PPS clock (the top signal)

The outputs have by default 50% duty cycle unless you changed the duty cycle.

You can enable Reference Synchronization feature. This shortens significantly the lock time after power up. But if the DPLL locks, then the 1PPS becomes invalid, then becomes valid back, the lock time will be determined by the slew rate limiter, which by default is set to 100.7us/s. If the initial phase offset between 1PPS and 1Hz output is 500ms, it will take 500/100.7E-3 seconds to lock. You can increase the slew rate limit to the max, that is around 4ms/s, which will make the DPLL to function most of the time to its natural speed.

Petre

Hello Petre,

thank you  for your swift response. I meant to attach the setup file in the previous post, but seemingly forgot to do it. You can find it attached now.

Yes we are currently using our own board (loading the REGMAP from the config file with a RPi) as availability of the eval board is rather limited compared to the older AD9548 we used. But i got a quote for it now, however, i might still try to fit the current board to your described scenario to test it out, as i should have enough space on the PCB for moving it around.

Is there any particular (maybe architectural) reason for the recommendation of using a crystal besides the OCXO, instead of just the OCXO?

I am eager to understand this PLL and its behaviour better, and with the previous one (which had a similar architecture with the DPLL, but no APLL), it was recommended to use the OCXO as the systems clock.

The duty cycle problem was cleared up, it indeed was set to "duty cycle mode". Since then we reset it to phase adjust and to 0. Also thanks to reminding me of the slew rate limiter.

Your example output looks really good! I am hopeful to achieve similar performance, but i am currently looking at >100uS of delay between Input and Output, which seems really wrong.

Please let me know if you notice anything wrong about the config file. Thank you very much for your help and support.

Best wishes

Matthias

AD9546_setup_1hz_in_1hz_out.json.txt

Hi,

let me comment first on your json file and then I'll respond to your questions.

1) You need to use the Configuration Wizard first and always do changes in the GUI only for things that cannot be set in the Wizard. In the Wizard, you only have REFA=10MHz set, but then in the GUI you also set REFBB=1Hz. This is not correct. The Wizard gave you an error in DPLL0 window. You should have gone back and set REFBB

2) After I have enabled REFBB=1Hz, 1.8V CMOS in the Wizard, the DPLL0 error disappeared and I clicked Load

After this, I focused on the DPLL0 settings in the GUI. I see you enabled Reference Synchronization, which is OK. But I recommend to get the DPLL0 going and locked first and then you can enable it to see how it speeds up the locking after power up. The reason is that if for some reason REFBB i snot valid, the outputs are not generated, which may be disconcerting.

Force Free run box was checked, which I am not sure why you wanted that.

Phase Slew Rate Limiter is at default, that is 100.7us/s, which is low. Decide what your application requires and set that slew rate limiter. I recommend starting with the max value, 2^32-1=4,294,967,295 ps/s= approx 4.3 ms/s, which will make the DPLL0 to function for most of the time at its natural slew rate.

For REFBB, the validation timer is set to default, 10ms. For a 1 Hz clock, it should be at least 1000 ms. The phase lock detection setting is 700 ps, which means that at DPD level, the DPLL will try to lock until the difference between REFBB and OUT0A feedback is less than 700ps. This requires a very good 1PPS clock. I recommend starting at 2000 ps, get the DPLL0 locked, learn how it functions and then go back to 700 ps. You may also want to increase the fill/drain rates up from 10. Start with 100 because the DPD functions every 1sec and this means the bathtubs will be filled from -2048 to +2048 in 400sec.

OUT0A and OUT0B are set as CML, OUT0C as HCSL. Note that on the eval board, all outputs are HCSL.

 AuxDPLL is set correctly. I suppose REFA=10MHz is a OCXO or TCXO, so you should be good here.

"Is there any particular (maybe architectural) reason for the recommendation of using a crystal besides the OCXO, instead of just the OCXO?"

The best phase noise performance is obtained when the doubler in the system clock PLL is enabled. The doubler requires the clock input to be exactly 50% duty cycle, which is guaranteed only if using a crystal resonator with the maintaining amplifier. The OCXO or TCXO have 45% to 55% duty cycle specification, which means the doubler must be disabled.

Petre

Hello Petre,

thank you very much for your response. Thanks for the tips about how to use the software and to use the wizard, as i did experience some weird behaviour and multiple crashes with it before, which was frustrating. I think it might not have been a correctly set up Setup file, as i didnt meant to use REFBB but rather REFB (which was also active?).

Anyway, I sadly only had a 25MHz SMD Crystal at hand, which is among the lowest frequencies still accepted by the AD9546. I manages to make it fit and to connect  the OCXO to REFA which i had broken out as a testpin.

After remaking the config file properly with your recommendations, i managed to finally get good performance of <=2ns (as i've set phase lock detection to 2ns).

Sadly, i didnt try to remake the config before adding the crystal, so it is not quite known if the problem of really bad phase lock detection (as it detected a lock with 200us difference) came from my config (most probable) or the non-recommended layout without the AuxDPLL.

Thank you very much for your help, also for the information about the phase noise being dependent on the duty cycle of the clock!

I've attached my config for reference. It should be pointed out, that im using 4-Wire SPI

/cfs-file/__key/communityserver-discussions-components-files/328/AD9546_5F00_1Hz_5F00_20241011.json.txt

Best wishes

Matthias Nowak