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Output continuously even when the ref is power off

Category: Hardware
Product Number: AD9544

We use a AD9544 to output a square wave with frequency equal to the ref A.

When the PLL locked, it output a square wave same frequency with ref A.  Then we turn off the ref A, there is still square wave in the PLL output. IS it normal?

We see the PLL can continuously change the output according to ref input. The AD9544 is special or everyone is designed like that. when the ref is turn off, the output continuously as last locked.

Regards.

zhang 

Parents
  • HI,

    the AD9544 (and all the AD9545 family of chips)  was designed to maintain a clock of a certain frequency (that you decide in the Configuration Wizard in ACE) whatever happens to the reference clock associated with the DPLL profile.

    If you want the outputs to turn off when the reference becomes invalid, you have the controller to monitor the reference status (through an interrupt for example) and mute the outputs. See Output Muting section at page 65, rev C AD9545 data sheet.

    Petre

  • Hi,

    We assume that there are three working steps:
    1. The clock configuration output is 7908Hz, and there is no output without a reference clock input. When the reference clock RFBB frequency input to AD9545 is 7907-7909Hz, will the frequency of the output clock change with the variation of the reference clock frequency? Or fixed at 7908Hz?
    2. When the PLL of AD9545 is in a locked state and we disconnect the reference clock RFBB,  AD9545 still has output at the frequency set in ACE.
    3. Input the reference clock RFBB again. If the frequency range of the reference clock is between 7905-7907Hz (within the effective range of RFBB set in ACE, but different from the previous frequency range of 7907-7909Hz), is the output frequency of AD9545 7908Hz or 7905-7907Hz?

    That is to say, within the effective frequency range of RFBB, Can AD9545 continuously track the reference clock frequency of RFBB and output a clock of the same frequency? Even if RFBB fails for a period of time and becomes valid again, AD9545 can still track the effective RFBB frequency.

    Thanks.

Reply
  • Hi,

    We assume that there are three working steps:
    1. The clock configuration output is 7908Hz, and there is no output without a reference clock input. When the reference clock RFBB frequency input to AD9545 is 7907-7909Hz, will the frequency of the output clock change with the variation of the reference clock frequency? Or fixed at 7908Hz?
    2. When the PLL of AD9545 is in a locked state and we disconnect the reference clock RFBB,  AD9545 still has output at the frequency set in ACE.
    3. Input the reference clock RFBB again. If the frequency range of the reference clock is between 7905-7907Hz (within the effective range of RFBB set in ACE, but different from the previous frequency range of 7907-7909Hz), is the output frequency of AD9545 7908Hz or 7905-7907Hz?

    That is to say, within the effective frequency range of RFBB, Can AD9545 continuously track the reference clock frequency of RFBB and output a clock of the same frequency? Even if RFBB fails for a period of time and becomes valid again, AD9545 can still track the effective RFBB frequency.

    Thanks.

Children
  • HI,

    "will the frequency of the output clock change with the variation of the reference clock frequency? Or fixed at 7908Hz?"

    The output will remain nominally fixed at 7908 Hz. I say that the output frequency is nominally at 7908 Hz because for example, in free run, the precision of the output depends on the accuracy of the system clock and in time on its stability. The output frequency is as exact as the reference clock is relative to the nominal reference clock when DPLL is locked.

    The reason is that the AD9545 has a DPLL+APLL architecture in which the APLL works to maintain the output frequency independent of what happens with the DPLL. Then you have the buildout and hitless modes that determine how the phase of the output behaves when the reference is switching or when the DPLL locks. The DPLL+APLL architecture is different from a pure APLL architecture. Choose the mode you want the DPLL to lock based on the phase behavior you need when the reference is switching or when the DPLL locks. See Translation modes section at page 85 in rev C AD9545 data sheet

    " When the PLL of AD9545 is in a locked state and we disconnect the reference clock RFBB,  AD9545 still has output at the frequency set in ACE.

    Yes.

    "If the frequency range of the reference clock is between 7905-7907Hz (within the effective range of RFBB set in ACE, but different from the previous frequency range of 7907-7909Hz), is the output frequency of AD9545 7908Hz or 7905-7907Hz?"

    7908Hz, nominally.

    "That is to say, within the effective frequency range of RFBB, Can AD9545 continuously track the reference clock frequency of RFBB and output a clock of the same frequency?"

    The output frequency does not change from the nominal value. 

    Petre