PLL1 not locking for REF A input.

Question

Hello, 
 I powered ON the AD9523 board, configured and selected input from REF B, now both the PLLs are locking and getting "EB" as a response from 0x22C register, with this locking condition, I selected REF A as input,then also getting "EB" response and both the PLLs are locking. Now, I power off and ON again, configured and selected input from REF A, then the response is "EA" from 0x22C register. i.e. here the problem I'm facing is as an initial state with REF A selection, getting "EA" response other wise the response is "EB" only. kindly help me in resolving this issue.

pminc48 · Accepted Answer

HI, 
 " I selected REF A as input,then also getting "EB" response and both the PLLs are locking . " 
 I am not convinced this statement is true because if REFA is the reference clock of PLL1, bit 2 of register 0x22C should have been 1 and the register should have been equal to 0xEF. 
 If REFA is not valid, (i.e. bit 2 is cleared to 0), then PLL1 cannot lock and bit 0 should be 0 as well. 
 So my suggestion is to look at the REFA clock as the chip does not see it as valid. Make sure the setting on the board matches the setting in the configuration software 
 Petre)

pminc48 · Answer

HI, 
 please use only one email trail to ask questions. Sending twice the same question in two different places does not make sense as they arrive always at me. 
 This is discussed here: RE: PLL2 is not locking 
 Petre

pminc48 · Answer

HI, 
 
 let me recapitulate: 
 - When REFA=100MHz, this clock comes from another AD9523-1. What format is this clock? The PLL1 does not lock 
 - When REFA=10MHz (?) from FOX924B-10.000, PLL1 locks 
 When I loaded Ref_A_Ref_Bconfiguration.txt file into the evaluation software, REFA divider is equal to 1, while REFB divider is equal to 4. So if you apply 100MHz, the PLL1 does not lock because it expects 2.5MHz. 
 Set REFA divider to 40 and the PLL1 should lock onto REFA=100MHz 
 
 Petre

pminc48 · Answer

Hi, 
 The AD9523-1, rev A data sheet provides at Table 4, page 7 the specifications of the differential and single ended reference clocks. 
 Put the scope probe on the REFA pins and see if the 100 MHz clock you provide there meets these specifications. 
 Instead of providing the clock from another AD9523-1, provide it from a signal generator. 
 Petre

AnandP · Answer

Hello Petre, 
 Thank you for your suggestions. By feeding REF A with other signal generator PLL1 is locking. and now this board is perfectly locking both the PLLs with both the references.

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PLL1 not locking for REF A input.