PLL1 not locking for REF A input.

HI,

"I selected REF A as  input,then also getting "EB" response and both the PLLs are locking."

I am not convinced this statement is true because if REFA is the reference clock of PLL1, bit 2 of register 0x22C should have been 1 and the register should have been equal to 0xEF.

If REFA is not valid, (i.e. bit 2 is cleared to 0), then PLL1 cannot lock and bit 0 should be 0 as well.

So my suggestion is to look at the REFA clock as the chip does not see it as valid. Make sure the setting on the board matches the setting in the configuration software

Petre

Hello Petre,

In our customized board, Reference selection is given in hardware i.e. there is one reference selection pin, if I make it low (i.e. reference select pin connected to ground) then REF A is selected otherwise it will take input from REF B. For REF B input there is an on board 10 MHz crystal, and for REF A 100 MHz input is providing from the external source.so, in this case at a time only one reference would be selected.  and in case of  REF B it is okay to get "EB" response. in case of REF A we should get "E7" but it is giving response as "EA" at 0x22C register.  Here, I'm providing the register map file for your reference.

"AD9523 Regmap File"
"Rev.","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","10000001","81"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","00000001","01"
"0011","00000000","00"
"0012","00000100","04"
"0013","00000000","00"
"0014","00000001","01"
"0015","00000000","00"
"0016","00101000","28"
"0017","00000000","00"
"0018","00001100","0C"
"0019","00011111","1F"
"001A","00010010","12"
"001B","00010110","16"
"001C","10010000","90"
"001D","00000000","00"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","00000111","07"
"00F1","10000111","87"
"00F2","00010011","13"
"00F3","00000010","02"
"00F4","01000000","40"
"00F5","00000000","00"
"00F6","00000000","00"
"00F7","00000001","01"
"00F8","00000000","00"
"00F9","00000000","00"
"00FA","00000000","00"
"0190","01110011","73"
"0191","00001001","09"
"0192","00000100","04"
"0193","00100000","20"
"0194","00011111","1F"
"0195","00000100","04"
"0196","01001000","48"
"0197","01100011","63"
"0198","00000000","00"
"0199","01110110","76"
"019A","00011111","1F"
"019B","00000100","04"
"019C","01001000","48"
"019D","01100011","63"
"019E","00000000","00"
"019F","00100000","20"
"01A0","00011111","1F"
"01A1","00000100","04"
"01A2","00100000","20"
"01A3","00011111","1F"
"01A4","00000100","04"
"01A5","00100000","20"
"01A6","00011111","1F"
"01A7","00000100","04"
"01A8","01100110","66"
"01A9","00001001","09"
"01AA","00000100","04"
"01AB","01001001","49"
"01AC","01100011","63"
"01AD","00000000","00"
"01AE","01001001","49"
"01AF","01100011","63"
"01B0","00000000","00"
"01B1","01101000","68"
"01B2","00001001","09"
"01B3","00000100","04"
"01B4","01101000","68"
"01B5","00001001","09"
"01B6","00000100","04"
"01B7","01010110","56"
"01B8","00001001","09"
"01B9","00000000","00"
"01BA","00000000","00"
"01BB","00000000","00"
"022C","00000000","00"
"022D","00000000","00"
"022E","00000000","00"
"022F","00000000","00"
"0230","00000000","00"
"0231","00000001","01"
"0232","00001101","0D"
"0233","00000000","00"
"0234","00000001","01"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00101011","2B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000011","03"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"

Hello Petre,

sorry for understanding the concept incorrectly. now,  0x22C is "EF" for REF B input, but "EE" for REF A input (i.e. PLL1 is not locking). kindly, suggest for PLL1 also locking with REF A input.   

HI,

please use only one email trail to ask questions. Sending twice the same question in two different places does not make sense as they arrive always at me.

This is discussed here:  RE: PLL2 is not locking 

Petre

hello,

sorry,but I'm facing 2 different issues in 2 different boards, that's why I posted 2 questions.

Hello,

In our customized board, REF B is 10MHz input, taking from onboard crystal oscillator (i.e. FOX924B-10.000). REF A is 100MHz input is taking from another AD953-1 board(let's say it as clock generator board). if I select REF B , both the PLLs are locking. later I selected REF A,PLL1 is not locking. now what I have done is,I fed FOX924B-10.000 crystal oscillator signal to REF A and selected REF A input,now both the PLL's got locked. when I feed the REF A with the signal from clock generator board, PLL1 is not locking. kindly, suggest me to lock the PLL1 in REF A input also.

HI,

let me recapitulate:

- When REFA=100MHz, this clock comes from another AD9523-1. What format is this clock? The PLL1 does not lock

- When REFA=10MHz (?) from FOX924B-10.000, PLL1 locks

When I loaded Ref_A_Ref_Bconfiguration.txt file into the evaluation software, REFA divider is equal to 1, while REFB divider is equal to 4. So if you apply 100MHz, the PLL1 does not lock because it expects 2.5MHz.

Set REFA divider to 40 and the PLL1 should lock onto REFA=100MHz

Petre

Hello,

pminc48 said:

When REFA=10MHz (?) from FOX924B-10.000, PLL1 locks

Yes,

pminc48 said:

When REFA=100MHz, this clock comes from another AD9523-1. What format is this clock? The PLL1 does not lock

 exactly, I'm also having doubt about the format,in what format should I have to feed such that PLL1 locks. and I also tried with REF A divider to 40, still PLL1 is not locking.  

And there is a small modification I have done with Ref_A_Ref_Bconfiguration.txt file i.e. at Input receivers configuration, I enabled REF A receiver and also REF A SE Negative input pin mode.

Hi,

The AD9523-1, rev A data sheet provides at Table 4, page 7 the specifications of the differential and single ended reference clocks. 

Put the scope probe on the REFA pins and see if the 100 MHz clock you provide there meets these specifications.

Instead of providing the clock from another AD9523-1, provide it from a signal generator.

Petre

Hello Petre,

Thank you for your suggestions. By feeding REF A with other signal generator PLL1 is locking. and now this board is perfectly locking both the PLLs with both the references.