AD9522-1
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The AD9522-11 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip...
Datasheet
AD9522-1 on Analog.com
Hello
In the LVDS Channel Dividers settings, set the LVDS output to a fixed state.
Divider 0 ignore SYNC :1
Divider o force high :0
After that, if you set Divider 0 ignore SYNC to 0, the output will be L,
but how long will it take after the settings are latched?
Thank you.
Hi,
To make the Divider 0 ignore SYNC signal, you set bit 6 in register 0x191 to 1.
Then you also set bit 5 (Divider 0 Force high) to force the divider output to be high.
There is also the bit 4 (Divider 0 Start High) that determines the polarity of the output when it starts to toggle.
You say that after you set these bits, the output was low.
I played with these three bits on an evaluation board and I can confirm the output stays low when the two bits 6 and 5 are set to 1.
Then, once the bit 6 is cleared to 0, I saw the output is toggling following the bit 4 setting.
So it is bit 4 that determines the polarity of the clock when it starts toggling. When the bits 6 and 5 are set to 1, the output is static low. It cannot be made to be static high.
"how long will it take after the settings are latched?"
It is hard for me to measure the delay between clearing bit 6 and the moment the output is generated.
The data sheet provides this propagation delay between the divider and the output. The timing then between the chip executing the clearing of bit 6 and generating an output should not be very far from the numbers below.
Petre
