Using the above equation I have Rset to be ~612kohm to get ~50ms delay. Following the below DivCode of #4. I am using a NDIV of 4096.
My input is 3.3V.
Not getting any output.
LTC6994-1
Production
The LTC6994 is a programmable delay block with a range of 1µs to 33.6 seconds. The LTC6994 is part of the TimerBlox® family of versatile silicon timing...
Datasheet
LTC6994-1 on Analog.com
Using the above equation I have Rset to be ~612kohm to get ~50ms delay. Following the below DivCode of #4. I am using a NDIV of 4096.
My input is 3.3V.
Not getting any output.
Hello Sean,
if you have a problem with a simulation, it is always a good idea to attach the simulation file. Then others can reproduce the problem and look for solutions.
In your case there is no simulation problem, the IC works as specified. The LTC6994-1 will delay either the rising edge or the falling edge of the signal, not both edges. It depends on the MSB of the DIV-Code.
In your case the rising edge is delayed by 50ms, the falling edge is not delayed. Your input pulse has only a high-time of 40ms. The falling edge at the input occurs before the delayed rising edge has reached the output. So the complete input pulse has to be filtered out. (The LTC6994 is also marketed as debouncer - with your setting the 40ms pulse at the input is assessed as bouncing or glitch and filtered).
Increase your puls high time at the input to 60ms, and you'll see a 10ms pulse at the output.
best regards
Achim
The datasheet(page 4) says the minimum recognized input pulse width is 5ns. So a 40ms pulse should have no problem being recognized, right?
LTC6994.ascAnd this demo has an input pulse with an on time of 40ms. It is going into the falling edge LTC6994-1, so why would that change when going into the rising edge LTC6994-1.
LTC6994.ascAnd this demo has an input pulse with an on time of 40ms. It is going into the falling edge LTC6994-1, so why would that change when going into the rising edge LTC6994-1.
Hi,
Thanks, Achim for your input. You are right.
Hi Sean,
The simulation file you have attached delays the falling edge of the input signal at first. Then delay the rising edge at the second stage. In the middle stage, pulse width is around 90ms. So delaying the rising edge of the signal doesn't eliminate the signal.
Thanks,
Emrecan
The datasheet(page 4) says the minimum recognized input pulse width is 5ns. So a 40ms pulse should have no problem being recognized, right?
Hello Sean,
thank you for the asc-file.
The datasheet(page 4) says the minimum recognized input pulse width is 5ns. So a 40ms pulse should have no problem being recognized, right?
maybe you misunderstand the functionality of the IC. The chip is made e.g. for debouncing mechanical buttons. If you set the parameters like you do in the simu, it is the main job of the IC to suppress pulses which are shorter than the delay time. It is made to suppress bounces and glitches - an so it supresses your 40ms pulse.
If you should be familiar with the delay-types in VHDL: this chip generates an inertial delay (not a transport delay)
Are you looking for a chip that delays any kind of signal sequence at the input by a certain time and then outputs it identically? That will not work with the LTC6994-1.
The LTC6994-2 comes closer to this (as it delays both edges). But also the LTC6994-2 will suppress pulses which are shorter than the delay time. The LTC6994 is a "Noise Discriminators/Pulse Qualifier". It is not an adjustable delay line.
best regards
Achim
Ya you are right, I did not understand the IC very well. I appreciate the information. Thank you!
I am going to use the LTC6994-2 part.