HMC7044_about the Wiki Example usage

Hi, 

N2 and R2 dividers are calculated by using VCXO frequency and PLL2 frequency parameters. To achieve better phase noise, the Software tried to enable the OSCIN doubler or keep the R2 value equal to 1 if possible. If not, PFD frequency is tried to be set to the greatest common divider of the output channels. 

PLL2 PFD frequency = VCXO Frequency * 2 (if Doubler enabled) / R2 divider

N2 Divider = PLL2 Frequency / PLL2 PFD Frequency

Unfortunately, ADISimCLK doesn't support 4-clock input capability.

You can control prescaler values and R1 and N1 divider values from the below screen of the GUI: 

Thanks,
Emrecan

Hi Emrecan,

Thank you for your reply.But I still wonder as the code indicated,the output 1 which is the divider is 3840,Is the frequency of it ouput is 768 kHz?Like 2949120000/3840=768000.It suppose to be 3.84MHz in my opinion.How it calculate? 

Hi, 

The output frequency is PLL2 Frequency divided by channel divider. In this case,  2949120000/3840=768000 for Output 1. 

You can modify and call the "hmc7044_clk_set_rate" function to set the desired output frequency.  i.e. hmc7044_clk_set_rate(hmc7044_device, 1, 3840000), in this case, the output divider is calculated as 768. 

Thanks,

Emrecan

Hi Emrecan,

thank you very much.

Best wishes!

Lcy0110