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Necessity to use External reference clock for PLL1 of AD9528

Category: Hardware
Product Number: AD9528

Hello All

We are using AD9528 to generate device clock and sysref required by ADRV9008-2 which is working at sampling rate of 245.76MHz. The Modulator in baseband (implemented on ZCU102) is working at the same sampling rate and the corresponding modulated output is being provided to DAC (here ADRV9008-2). When the output of DAC in terms of constellation is observed in spectrum analyzer, it is stable for QPSK modulated data, however for higher modulation i.e. for 8-PSK and above, the constellation is not stable and worst EVM ( > 3%) is observed. This issue was not observed when an external reference clock of 30.72MHz (as suggested in was provided to PLL1 of AD9528. Our main concern is not to use this external clock across TX path. Is there any way to avoid using this reference clock so that we get a stable TX performance in terms of constellation and EVM.

Thanks in advance


  • HI,

    Please post this question to the ADRV9008-2 forum because it is a question about the AD9528 in the context of using it with the ADRV9008-2 and is referencing specifications related to the ADRV9008-2, not the AD9528.

    I also recommend writing the ADRV9008-2 as product number, not the AD9528


  • Hello  

    As per your suggestion, I had created a new thread in ADRV9008-2 forum : 

    However, I was asked to post this question in Ad9528 forum.

    Idea is to use AD9528 in Single Loop Mode (PLL1, REFA and REFB inputs to AD9528 are off) and so, the following changes were done in app_clocking.c file of AD, where the following parameters were changed : 

    ad9528_param.pdata->refa_en = 0;// earlier it was set to 1;

    ad9528_param.pdata->refa_diff_rcv_en = 0;//  --earlier set to 1
    ad9528_param.pdata->refa_r_div = 0;//1; --earlier set to 1

    ad9528_param.pdata->pll1_bypass_en = 1;//0;      --earlier set to 0

    However, on making these changes, the constellation was found stable for a short time and rotations were still observed. The code snippet is with necessary changes for single loop mode is attached for reference.

    // ad9528 settings
    	ad9528_param.pdata->spi3wire = 0;
    	ad9528_param.pdata->vcxo_freq = 122880000;
    	ad9528_param.pdata->refa_en = 0;//1;       --earlier set to 1
    	ad9528_param.pdata->refa_diff_rcv_en = 0;//1;       --earlier set to 1
    	ad9528_param.pdata->refa_r_div = 0;//1;    --earlier set to 1
    	ad9528_param.pdata->osc_in_cmos_neg_inp_en = 1;
    	ad9528_param.pdata->pll1_feedback_div = 4;
    	ad9528_param.pdata->pll1_feedback_src_vcxo = 0; /* VCO */
    	ad9528_param.pdata->pll1_charge_pump_current_nA = 5000;
    	ad9528_param.pdata->pll1_bypass_en = 1;//0;      --earlier set to 0
    	ad9528_param.pdata->pll2_vco_div_m1 = 3;
    	ad9528_param.pdata->pll2_n2_div = 10;
    	ad9528_param.pdata->pll2_r1_div = 1;
    	ad9528_param.pdata->pll2_charge_pump_current_nA = 805000;
    	ad9528_param.pdata->pll2_bypass_en = false;
    	ad9528_param.pdata->sysref_src = SYSREF_SRC_INTERNAL;
    	ad9528_param.pdata->sysref_pattern_mode = SYSREF_PATTERN_CONTINUOUS;
    	ad9528_param.pdata->sysref_req_en = true;
    	ad9528_param.pdata->sysref_nshot_mode = SYSREF_NSHOT_4_PULSES;
    	ad9528_param.pdata->sysref_req_trigger_mode = SYSREF_LEVEL_HIGH;
    	ad9528_param.pdata->rpole2 = RPOLE2_900_OHM;
    	ad9528_param.pdata->rzero = RZERO_1850_OHM;
    	ad9528_param.pdata->cpole1 = CPOLE1_16_PF;
    	ad9528_param.pdata->stat0_pin_func_sel = 0x1; /* PLL1 & PLL2 Locked */
    	ad9528_param.pdata->stat1_pin_func_sel = 0x7; /* REFA Correct */

    Requesting your suggestions on how to operate AD9528 in single loop mode, so that I get a stable clock.


  • HI,

    I'm sorry you entered in a ping pong match with apps engineers.

    I do not know the files you are talking about because I do not support the ADRV9009. However, looking at the lines of code, I deducted the following:

    - you do not want to use PLL1. This is OK

    - VCXO=122.88MHz, sent on the VCXO_IN_N pin. This is like on the evaluation board.

    - PLL2 seems to have been configured as below, which is OK

    - I do not know the output clock frequencies, so I do not know what distribution dividers you want to use. But this is fine.

    You say: "on making these changes, the constellation was found stable for a short time and rotations were still observed.".

    I do not know what constellation and their rotations mean, but I suppose you blame AD9528 PLL2 for them. If this is the case, you can check the register 0x0508 of the AD9528 to see if bit 1 is 1 (PLL2 has locked) or 0 (PLL2 has not locked).

    Make sure in the code you have there is a line that starts the PLL2 VCO calibration: bit 0 in register 0x0203 is set to 1. There also must be a IO UPDATE operation executed after (register 0x000F is written with value 0x01). Then you should read bit 0 of register 0x0509 to see when the calibration ends and then you clear the bit 0 in register 0x0203 to 0.

    This should make the PLL2 lock. When you say the constellation is not stable after a short time, verify the PLL2 is still locked. If it is, then the problem is not with the AD9528. If it is not, try first to increase the charge pump current to the max value, 893.5 uA in the eval software, which may mean changing 805000 in this line into 893500:

    ad9528_param.pdata->pll2_charge_pump_current_nA = 805000;

    If even after this line the PLL2 looses lock, it signifies you have a problem with the VCXO and you'll have to change it.


  • Hi Petre

    Sorry for providing rudimentary information.

    We are using ADRV9008-2 evaluation board which has on-board AD9528 chip along with Crystek VCXO connected to it. AD9528 is configured to provide output frequency of 122.88MHz.

    "I do not know what constellation and their rotations mean"- Constellation here means that we are modulating data with 256-APSK scheme and the corresponding vector plot is observed in spectrum analyzer to calculate Error Vector Magnitude (EVM). The EVM observed with external reference clock seems to be within 1% which is the most acceptable value for effective demodulation , however it increases when reference clock (REFA) is not provided to AD9528. 

    Thanks for your valuable suggestions. As said, will check the status of PLL2 VCO and make necessary changes as required.


  • Hi,

    because you said the output is 122.88MHz, the same frequency of the VCXO, this means the distribution divider on the 122.88MHz output is 10, equal to the PLL2 feedback divider. Because the SYNC signal resets both of these dividers, it means the 122.88MHz output is in phase to the VCXO input, making the PLL2 to act in an equivalent zero delay mode. This is very useful if you want to align the outputs of multiple AD9528s.

    Please keep me posted on the developments