Square wave and amplitude control of IOUTN and IOUTP

Hi Sumeet6 ,

Controlling the amplitude of the current output (IOUT) is configurable in the AD9102 registers. It can be modified in various ways:

• Modifying the DAC digital gain (Register 0x35)
• Modifying the band-gap voltage (Register 0x03). Note that the
• Modifying RSETx resistors - only if-using on-chip RSET (Register 0x0C)

Note that there are limits in the range of the amplitude, and the resulting voltage out the AD9102 must still be within output compliance as seen in Table 1 and 2.

For your second question, square waves can be generated with the AD9102 using the SRAM. You can store square wave vectors then the AD9102 will generate them. Note that the SRAM has 4096 addresses. The longer the waveform you will store, the more SRAM addresses will be written into and the longer it will take to store the values in SRAM. This is one thing to consider depending on your system's speed requirement to change the duty cycle of the square wave.

Best regards,

Marco

Hello Marco,

Thank you for your answers, I need to connect a DAC output to REFIO pin to control amplitude of IOUT pin, Is it okay to connect that to it?
How can generate square wave or other type of waveform vector tables? Is there a software that can generate this vector table for me? 

Please let me know, thank you.

Hello Marco,

Thanks for your reply, Yes DAC output would be positive constant voltage which i will be varying from 0.1V to 1.2Volts to control IOUT N/P amplitudes.

My lower frequency limit is 100Hz and I need to generate tones from 100Hz to 13.5KHz, can you suggest me what should be my clock frequency. 

Hi Sumeet6 ,

The DDS_VREF must be constant to 1 V, it cannot be varying from 0.1V to 1.2V because if it's varying, there may be cases where there is no output out of the AD9102 because REFIO is too small. As mentioned, the full-scale output of AD9102 is based on VREFIO (typically 1V) and the RSET resistor (typically 8kΩ). 

You can try using a clock frequency of 400kHz. It can accommodate 100 Hz to 13.5 kHz with 4000 SRAM addresses. 

Best regards,
Marco

Hello Marco,

Thank you for your insight, let say I keep REFIO voltage at 1 V, but I connect a digital pot at RSET resistor, will I be able to change the amplitude, or only way to control amplitude is by changing internal RSET values and DAC digital gain?

When I put a 400 kHz as clock in vector generator, it shows that desired frequency as 13.133 kHz instead of 13.5 kHz. Why is it so? It shows record length of 30 at 13.5 kHz, whereas with 400 kHz clock I get exact clock of 100 Hz. And when I put 2000 Hz as desired frequency, I get actual frequency as 2049.XXXX Hz, is there any way by which I get accurate 1 Hz steps?

Please let me know,

Thank you and BR,

Sumeet

Hi Sumeet6 ,

We will have to confirm this on bench (adjustment of IOUTFS if REFIO is varying). For now it's recommended to control the amplitude by modifying RSET resistor (either on-chip or external RSET) or utilizing the DAC digital gain. The internal VREFIO has limits of only ±20% of the nominal band-gap voltage of 1V so using an external reference voltage may pose the same limits. Exceeding these limits may result to no output out of the DAC. 

For the vector generator, the "Actual frequency" is adjusted to the closest frequency that allows the generation of a coherent signal based on the set record length - i.e. continuous from the last sample to the first sample. I unchecked the "Minimize Record Length" box and set the Record Length to 4000. I set the desired frequency to 100 Hz and 13.5kHz and the actual frequency was the same as what I set.

However, the resulting actual frequencies in between (in resolution of 1 Hz steps) will not be exactly equal to the desired frequencies if the Record length is made constant to 4000. The record length (i.e. the number of SRAM addresses to be used) will have to be modified to set the actual frequency equal to the desired frequency. For instance, 13.4 kHz actual frequency will need 2000 Record length instead of the 4000 at 400kHz DAC CLK. For other frequencies, the minimum record length might exceed 4096 (Recall that AD9102 has 4096 SRAM addresses only).

You can play around with the parameters in ACE Vector Generator Tool as well as refer to the wiki user guide to get your desired frequencies. In essence, the 1 Hz steps is too high of a resolution for setting square waves in SRAM, which is why I'd recommend utilizing the on-chip DDS of AD9102 then convert the sine waves to square waves externally. 

Best regards,
Marco 

Hello Marco,

Thanks for your reply. I tried playing with single tone generator with ACE software, but desired frequency is still off, if the resolution with this part is not possible, can you suggest me a suitable part that is capable of providing a 1 Hz resolution.

Hi Sumeet6 ,

I would suggest posting a query in the Precision DACs community. They might have waveform generators which could meet your requirements. The AD9102 is a High-speed DAC (up to 180 MHz DAC clock frequency). Higher resolutions in the output need lower speedgrade to have accuracy in the output, and AD9102 does not meet this requirement because it was originally designed for higher speed applications (e.g. Ultrasound). 

Just a question, what does your system look like? Would it be viable to have an FPGA instead of a DAC or DDS generate the square waves in your setup? 

Best regards,
Marco

Hello Marco,

Can on chip DDS give 1 Hz resolution, ADI DDS simulation tool gives good 1Hz relationship, am I missing something here?

For AD9102, yes the DDS can provide 1 Hz resolution. The resolution will depend on the DAC CLK. Please refer to page 23 of the datasheet. 

DDS is one of the Prestored waveforms in AD9102, along with Sawtooth, Pseudorandom noise, and DC constant. Square waves is not a Prestored waveform in AD9102 thus you will need to utilize the SRAM to generate a square wave. However, the SRAM is limited in size (4096 x 14-bit SRAM for AD9102) so there will be a limit to the kind of waveform you could generate with it. However, you can generate any arbitrary waveform, not just square waves. 

Hello Marco, 

I dont have a FPGA, I will be controlling the part through SPI from MCU, given the time frame I am working, FPGA solution will take lot of time for me, hence I am looking for DDS chip.

Thank you, Marco, for your explanation, just to confirm AD9102 is able to generate sine wave, sawtooth and triangular wave forms with resolution of 1 Hz since they are already available. Another thing pseudorandom generator noise waveform is also prestored, I can generate them with appropriate register setting in AD9102. Only for square waveform I will need generate vectors in SRAM, please let me know my understanding regarding this part is correct.

2. If I provide a precision voltage reference to REFIO pin whose voltage will be 1 V, then will DAC gain and internal RSET values I will be able to control the amplitude of the Sine wave which is created by DDS. I intend to amplify this signal to appropriate levels of 3.3V, so 100 mV would be 1 V and 300 mV will be around 3 V when I have a gain of 10. Is my understanding regarding this part, correct?

Thank you, Marco, for your explanation, just to confirm AD9102 is able to generate sine wave, sawtooth and triangular wave forms with resolution of 1 Hz since they are already available. Another thing pseudorandom generator noise waveform is also prestored, I can generate them with appropriate register setting in AD9102. Only for square waveform I will need generate vectors in SRAM, please let me know my understanding regarding this part is correct.

2. If I provide a precision voltage reference to REFIO pin whose voltage will be 1 V, then will DAC gain and internal RSET values I will be able to control the amplitude of the Sine wave which is created by DDS. I intend to amplify this signal to appropriate levels of 3.3V, so 100 mV would be 1 V and 300 mV will be around 3 V when I have a gain of 10. Is my understanding regarding this part, correct?

1. Yes this is correct.

2. What is the current you be generating out of the AD9102? Is it the 100-300mV? The nominal full-scale current out of the AD9102 is 4mA. With 250Ω load resistors the nominal output is 1V (or 2Vpp). Anything above +1V (output compliance of AD9102) and an amplifier must be used. 

I am closely following the evaluation board design with output stage resembling to that of evb board; I have connected 249 ohms resistance to differential pair which is then fed ADA4817 opamp, I believe the output of Opamp 4817 will be 5 volts when current drawn on IOUT pins will be 4 mA, I want to change the amplitude of IOUTN/P pins without exceeding 4 mA rating. 

Apologies I initially got confused with the part where you will be amplifying 100-300mV to 1-3V with a gain of 10. However, this should be doable. When the full-scale current is 4mA and there's 249 ohm load resistance on IOUTP/IOUTN, then the voltage output is ~1V. The 5V output out of the ADA4817-2 means there's a gain of 5.

The full-scale current on the AD9102 can be lowered to achieve the 100-300mV output and amplify it with a gain of 5 out of the ADA4817-2 to achieve 1-3V. This is still valid since it does not exceed the compliance range of the AD9102.

Best regards,
Marco