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different phases

Category: Hardware
Product Number: HMC7044

Hello,

I want to implement a clock distribution system for data converters, here is my setup:

  • A source produces two free running clocks at 1 GHz (CLK) and 1 MHz (SCLK), they are generated together so they have know and fixed phase relation
  • An HMC7044 is connected to the source
  • An FPGA can control the HMC digital inputs

The goal is to have deterministic phase relations between a specific SCLK edge and the output clocks of the HMC7044.

My idea is to do the following:

1) Power up the HMC, CLK and SCLK generation is already stable

2) Turn on RFsync buffer on the HMC to synchronize the internal SYSREF timer with the SCLK signal

3) Disable RFsync buffer, from now on local SYSREF is synchronized with SCLK

4) The FPGA, also connected to SCLK, chooses a specific rising edge and drives the GPI pin to 1 and then to 0 to enable a reseed request

Q: Is it possible to do so?

At the moment I observe the following:

After step 2 and 3, the fpga chooses a rising edge every ms and I see that there is fixed phase alignment between HMC outputs and SCLK an the input at every reseed request

If I repeat steps 2 and 3, then there is again a fixed phase alignment but this is different from the previous value.

# glbl_cfg1_swrst[0:0] = 0x0
dut.write(0x0, 0x0)

# glbl_cfg1_sleep[0:0] = 0x0
# glbl_cfg1_restart[1:1] = 0x0
# sysr_cfg1_pulsor_req[2:2] = 0x0
# pll1_cfg1_forceholdover[4:4] = 0x0
# glbl_cfg1_perf_pllvco[5:5] = 0x0
# dist_cfg1_perf_floor[6:6] = 0x0
# sysr_cfg1_reseed_req[7:7] = 0x0
dut.write(0x1, 0x0)

# sysr_cfg1_rev[0:0] = 0x0
# sysr_cfg1_slipN_req[1:1] = 0x0
# pll2_cfg1_autotune_trig[2:2] = 0x0
dut.write(0x2, 0x0)

# glbl_cfg1_ena_pll1[0:0] = 0x0
# glbl_cfg1_ena_pll2[1:1] = 0x0
# glbl_cfg1_ena_sysr[2:2] = 0x1
# glbl_cfg2_ena_vcos[4:3] = 0x0
# glbl_cfg1_ena_sysri[5:5] = 0x1
dut.write(0x3, 0x24)

# glbl_cfg7_ena_clkgr[6:0] = 0x3
dut.write(0x4, 0x3)

# glbl_cfg4_ena_rpath[3:0] = 0x3
# dist_cfg1_refbuf0_as_rfsync[4:4] = 0x1
# dist_cfg1_refbuf1_as_extvco[5:5] = 0x1
# pll2_cfg2_syncpin_modesel[7:6] = 0x1
dut.write(0x5, 0x73)

# glbl_cfg1_clear_alarms[0:0] = 0x0
dut.write(0x6, 0x0)

# glbl_reserved[0:0] = 0x0
dut.write(0x7, 0x0)

# glbl_cfg1_dis_pll2_syncatlock[0:0] = 0x1
dut.write(0x9, 0x1)

# glbl_cfg5_ibuf0_en[0:0] = 0x1
# glbl_cfg5_ibuf0_mode[4:1] = 0x1
dut.write(0xA, 0x3)

# glbl_cfg5_ibuf1_en[0:0] = 0x1
# glbl_cfg5_ibuf1_mode[4:1] = 0xA
dut.write(0xB, 0x15)

# glbl_cfg5_ibuf2_en[0:0] = 0x0
# glbl_cfg5_ibuf2_mode[4:1] = 0x3
dut.write(0xC, 0x6)

# glbl_cfg5_ibuf3_en[0:0] = 0x0
# glbl_cfg5_ibuf3_mode[4:1] = 0x3
dut.write(0xD, 0x6)

# glbl_cfg5_ibufv_en[0:0] = 0x1
# glbl_cfg5_ibufv_mode[4:1] = 0x3
dut.write(0xE, 0x7)

# pll1_cfg2_rprior1[1:0] = 0x0
# pll1_cfg2_rprior2[3:2] = 0x1
# pll1_cfg2_rprior3[5:4] = 0x2
# pll1_cfg2_rprior4[7:6] = 0x3
dut.write(0x14, 0xE4)

# pll1_cfg3_los_valtime_sel[2:0] = 0x3
dut.write(0x15, 0x3)

# pll1_cfg2_holdover_exitcrit[1:0] = 0x0
# pll1_cfg2_holdover_exitactn[3:2] = 0x3
dut.write(0x16, 0xC)

# pll1_cfg7_hodac_offsetval[6:0] = 0x0
dut.write(0x17, 0x0)

# pll1_cfg2_hoadc_bw_reduction[1:0] = 0x0
# pll1_cfg1_hodac_force_quickmode[2:2] = 0x1
# pll1_cfg1_hodac_dis_avg_track[3:3] = 0x0
dut.write(0x18, 0x4)

# pll1_cfg1_los_uses_vcxodiv[0:0] = 0x0
# pll1_cfg1_los_bypass_lcmdiv[1:1] = 0x0
dut.write(0x19, 0x0)

# pll1_cfg4_cpi[3:0] = 0x8
dut.write(0x1A, 0x8)

# pll1_cfg1_pfd_invert[0:0] = 0x0
# pll1_cfg1_cppulldn[1:1] = 0x0
# pll1_cfg1_cppullup[2:2] = 0x0
# pll1_cfg1_cpendn[3:3] = 0x1
# pll1_cfg1_cpenup[4:4] = 0x1
dut.write(0x1B, 0x18)

# pll1_cfg8_los_div_setpt_r0[7:0] = 0x4
dut.write(0x1C, 0x4)

# pll1_cfg8_los_div_setpt_r1[7:0] = 0x1
dut.write(0x1D, 0x1)

# pll1_cfg8_los_div_setpt_r2[7:0] = 0x4
dut.write(0x1E, 0x4)

# pll1_cfg8_los_div_setpt_r3[7:0] = 0x1
dut.write(0x1F, 0x1)

# pll1_cfg8_los_div_setpt_vcxo[7:0] = 0x4
dut.write(0x20, 0x4)

# pll1_cfg16_refdivrat_lsb[7:0] = 0x4
dut.write(0x21, 0x4)

# pll1_cfg16_refdivrat_msb[7:0] = 0x0
dut.write(0x22, 0x0)

# pll1_cfg16_fbdivrat_lsb[7:0] = 0x10
dut.write(0x26, 0x10)

# pll1_cfg16_fbdivrat_msb[7:0] = 0x0
dut.write(0x27, 0x0)

# pll1_cfg5_lkdtimersetpt[4:0] = 0xF
# pll1_cfg1_use_slip_for_lkdrst[5:5] = 0x0
dut.write(0x28, 0xF)

# pll1_cfg1_automode[0:0] = 0x1
# pll1_cfg1_autorevertive[1:1] = 0x0
# pll1_cfg1_holdover_uses_dac[2:2] = 0x1
# pll1_cfg2_manclksel[4:3] = 0x0
# pll1_cfg1_byp_debouncer[5:5] = 0x0
dut.write(0x29, 0x5)

# pll1_hoff_timer_setpoint[7:0] = 0x0
dut.write(0x2A, 0x0)

# pll2_reserved[7:0] = 0x1
dut.write(0x31, 0x1)

# pll2_cfg1_rpath_x2_bypass[0:0] = 0x1
dut.write(0x32, 0x1)

# pll2_rdiv_cfg12_divratio_lsb[7:0] = 0x2
dut.write(0x33, 0x2)

# pll2_rdiv_cfg12_divratio_msb[3:0] = 0x0
dut.write(0x34, 0x0)

# pll2_vdiv_cfg16_divratio_lsb[7:0] = 0x20
dut.write(0x35, 0x20)

# pll2_vdiv_cfg16_divratio_msb[7:0] = 0x0
dut.write(0x36, 0x0)

# pll2_cfg4_cp_gain[3:0] = 0xF
dut.write(0x37, 0xF)

# pll2_pfd_cfg1_invert[0:0] = 0x0
# pll2_pfd_cfg1_force_dn[1:1] = 0x0
# pll2_pfd_cfg1_force_up[2:2] = 0x0
# pll2_pfd_cfg1_dn_en[3:3] = 0x1
# pll2_pfd_cfg1_up_en[4:4] = 0x1
dut.write(0x38, 0x18)

# pll2_cfg1_oscout_path_en[0:0] = 0x0
# pll2_cfg2_oscout_divratio[2:1] = 0x0
dut.write(0x39, 0x0)

# pll2_cfg1_obuf0_drvr_en[0:0] = 0x0
# pll2_cfg5_obuf0_drvr_res[2:1] = 0x0
# pll2_cfg5_obuf0_drvr_mode[5:4] = 0x0
dut.write(0x3A, 0x0)

# pll2_cfg1_obuf1_drvr_en[0:0] = 0x0
# pll2_cfg5_obuf1_drvr_res[2:1] = 0x0
# pll2_cfg5_obuf1_drvr_mode[5:4] = 0x0
dut.write(0x3B, 0x0)

# glbl_cfg5_gpi1_en[0:0] = 0x0
# glbl_cfg5_gpi1_sel[4:1] = 0x0
dut.write(0x46, 0x0)

# glbl_cfg5_gpi2_en[0:0] = 0x0
# glbl_cfg5_gpi2_sel[4:1] = 0x0
dut.write(0x47, 0x0)

# glbl_cfg5_gpi3_en[0:0] = 0x0
# glbl_cfg5_gpi3_sel[4:1] = 0x4
dut.write(0x48, 0x8)

# glbl_cfg5_gpi4_en[0:0] = 0x1
# glbl_cfg5_gpi4_sel[4:1] = 0x9
dut.write(0x49, 0x13)

# glbl_cfg8_gpo1_en[0:0] = 0x0
# glbl_cfg8_gpo1_mode[1:1] = 0x1
# glbl_cfg8_gpo1_sel[7:2] = 0xD
dut.write(0x50, 0x36)

# glbl_cfg8_gpo2_en[0:0] = 0x0
# glbl_cfg8_gpo2_mode[1:1] = 0x1
# glbl_cfg8_gpo2_sel[7:2] = 0xC
dut.write(0x51, 0x32)

# glbl_cfg8_gpo3_en[0:0] = 0x0
# glbl_cfg8_gpo3_mode[1:1] = 0x0
# glbl_cfg8_gpo3_sel[7:2] = 0x0
dut.write(0x52, 0x0)

# glbl_cfg8_gpo4_en[0:0] = 0x0
# glbl_cfg8_gpo4_mode[1:1] = 0x0
# glbl_cfg8_gpo4_sel[7:2] = 0x0
dut.write(0x53, 0x0)

# glbl_cfg2_sdio_en[0:0] = 0x1
# glbl_cfg2_sdio_mode[1:1] = 0x1
dut.write(0x54, 0x3)

# sysr_cfg3_pulsor_mode[2:0] = 0x1
dut.write(0x5A, 0x1)

# sysr_cfg1_synci_invpol[0:0] = 0x0
# sysr_cfg1_pll2_carryup_sel[1:1] = 0x0
# sysr_cfg1_ext_sync_retimemode[2:2] = 0x1
dut.write(0x5B, 0x4)

# sysr_cfg16_divrat_lsb[7:0] = 0xFA
dut.write(0x5C, 0xFA)

# sysr_cfg16_divrat_msb[3:0] = 0x0
dut.write(0x5D, 0x0)

# dist_cfg1_extvco_islowfreq_sel[0:0] = 0x0
# dist_cfg1_extvco_div2_sel[1:1] = 0x0
dut.write(0x64, 0x0)

# clkgrpx_cfg1_alg_dly_lowpwr_sel[0:0] = 0x0
dut.write(0x65, 0x0)

# alrm_cfg4_pll1_los4_allow[3:0] = 0x0
# alrm_cfg1_pll1_hold_allow[4:4] = 0x0
# alrm_cfg1_pll1_lock_allow[5:5] = 0x0
# alrm_cfg1_pll1_acq_allow[6:6] = 0x0
# alrm_cfg1_pll1_nearlock_allow[7:7] = 0x0
dut.write(0x70, 0x0)

# alrm_cfg1_pll2_lock_allow[0:0] = 0x0
# alrm_cfg1_sysr_unsyncd_allow[1:1] = 0x0
# alrm_cfg1_clkgrpx_validph_allow[2:2] = 0x0
# alrm_cfg1_plls_both_locked_allow[3:3] = 0x0
# alrm_cfg1_sync_req_allow[4:4] = 0x1
dut.write(0x71, 0x10)

# glbl_ro8_chipid_lob[7:0] = 0x1
dut.write(0x78, 0x1)

# glbl_ro8_chipid_mid[7:0] = 0x52
dut.write(0x79, 0x52)

# glbl_ro8_chipid_hib[7:0] = 0x4
dut.write(0x7A, 0x4)

# alrm_ro1_alarm_masked_viaspi[0:0] = 0x1
dut.write(0x7B, 0x1)

# alrm_ro4_pll1_los4_now[3:0] = 0x0
# alrm_ro1_pll1_hold_now[4:4] = 0x0
# alrm_ro1_pll1_lock_now[5:5] = 0x0
# alrm_ro1_pll1_acq_now[6:6] = 0x0
# alrm_ro1_pll1_nearlock_now[7:7] = 0x0
dut.write(0x7C, 0x0)

# alrm_ro1_pll2_lock_now[0:0] = 0x0
# alrm_ro1_sysr_unsyncd_now[1:1] = 0x1
# alrm_ro1_clkgrpx_validph_now[2:2] = 0x0
# alrm_ro1_plls_both_locked_now[3:3] = 0x0
# alrm_ro1_sync_req_now[4:4] = 0x1
dut.write(0x7D, 0x12)

# alrm_ro4_pll1_los4_latch[3:0] = 0x0
# alrm_ro1_pll1_hold_latch[4:4] = 0x0
# alrm_ro1_pll1_acq_latch[5:5] = 0x0
# alrm_ro1_pll2_acq_latch[6:6] = 0x0
dut.write(0x7E, 0x0)

# pll1_ro3_fsm_state[2:0] = 0x0
# pll1_ro2_selected_clkidx[4:3] = 0x0
# pll1_ro2_bestclk[6:5] = 0x0
dut.write(0x82, 0x0)

# pll1_ro7_dac_avg[6:0] = 0x40
dut.write(0x83, 0x40)

# pll1_ro7_dac_current[6:0] = 0x3F
# pll1_ro1_dac_compare[7:7] = 0x0
dut.write(0x84, 0x3F)

# pll1_ro1_adc_outofrange[0:0] = 0x1
# pll1_ro1_adc_moving_quick[1:1] = 0x1
# pll1_ro1_lookslikelos_vcxo[2:2] = 0x0
# pll1_ro1_los_active_ref[3:3] = 0x0
dut.write(0x85, 0x3)

# pll1_ro5_eng_fullstate[4:3] = 0x0
dut.write(0x86, 0x0)

# pll2_ro8_tunestatus[7:0] = 0x10
dut.write(0x8C, 0x10)

# pll2_ro8_vtune_error_lsb[7:0] = 0xFF
dut.write(0x8D, 0xFF)

# pll2_ro8_vtune_error_msb[5:0] = 0x1F
# pll2_ro8_vtune_error_sign[6:6] = 0x0
# pll2_ro8_vtune_status[7:7] = 0x0
dut.write(0x8E, 0x1F)

# pll2_ro4_syncfsm_state[3:0] = 0x0
# pll2_ro4_atunefsm_state[7:4] = 0x0
dut.write(0x8F, 0x0)

# sysr_ro4_fsmstate[3:0] = 0x2
# grpx_ro1_outdivfsm_busy[4:4] = 0x0
dut.write(0x91, 0x2)

# reg_96[7:0] = 0x0
dut.write(0x96, 0x0)

# reg_97[7:0] = 0x0
dut.write(0x97, 0x0)

# reg_98[7:0] = 0x0
dut.write(0x98, 0x0)

# reg_99[7:0] = 0x0
dut.write(0x99, 0x0)

# reg_9A[7:0] = 0x0
dut.write(0x9A, 0x0)

# reg_9B[7:0] = 0xAA
dut.write(0x9B, 0xAA)

# reg_9C[7:0] = 0xAA
dut.write(0x9C, 0xAA)

# reg_9D[7:0] = 0xAA
dut.write(0x9D, 0xAA)

# reg_9E[7:0] = 0xAA
dut.write(0x9E, 0xAA)

# reg_9F[7:0] = 0x55
dut.write(0x9F, 0x55)

# reg_A0[7:0] = 0x56
dut.write(0xA0, 0x56)

# reg_A1[7:0] = 0x97
dut.write(0xA1, 0x97)

# reg_A2[7:0] = 0x3
dut.write(0xA2, 0x3)

# reg_A3[7:0] = 0x0
dut.write(0xA3, 0x0)

# reg_A4[7:0] = 0x0
dut.write(0xA4, 0x0)

# reg_A5[7:0] = 0x0
dut.write(0xA5, 0x0)

# reg_A6[7:0] = 0x1C
dut.write(0xA6, 0x1C)

# reg_A7[7:0] = 0x0
dut.write(0xA7, 0x0)

# reg_A8[7:0] = 0x22
dut.write(0xA8, 0x22)

# reg_A9[7:0] = 0x0
dut.write(0xA9, 0x0)

# reg_AB[7:0] = 0x0
dut.write(0xAB, 0x0)

# reg_AC[7:0] = 0x20
dut.write(0xAC, 0x20)

# reg_AD[7:0] = 0x0
dut.write(0xAD, 0x0)

# reg_AE[7:0] = 0x8
dut.write(0xAE, 0x8)

# reg_AF[7:0] = 0x50
dut.write(0xAF, 0x50)

# reg_B0[7:0] = 0x9
dut.write(0xB0, 0x9)

# reg_B1[7:0] = 0xD
dut.write(0xB1, 0xD)

# reg_B2[7:0] = 0x0
dut.write(0xB2, 0x0)

# reg_B3[7:0] = 0x0
dut.write(0xB3, 0x0)

# reg_B5[7:0] = 0x0
dut.write(0xB5, 0x0)

# reg_B6[7:0] = 0x0
dut.write(0xB6, 0x0)

# reg_B7[7:0] = 0x0
dut.write(0xB7, 0x0)

# reg_B8[7:0] = 0x0
dut.write(0xB8, 0x0)

# clkgrp1_div1_cfg1_en[0:0] = 0x1
# clkgrp1_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp1_div1_cfg2_startmode[3:2] = 0x0
# clkgrp1_div1_cfg1_rev[4:4] = 0x1
# clkgrp1_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp1_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp1_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0xC8, 0xF3)

# clkgrp1_div1_cfg12_divrat_lsb[7:0] = 0x4
dut.write(0xC9, 0x4)

# clkgrp1_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0xCA, 0x0)

# clkgrp1_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0xCB, 0x0)

# clkgrp1_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xCC, 0x0)

# clkgrp1_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xCD, 0x0)

# clkgrp1_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0xCE, 0x0)

# clkgrp1_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp1_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0xCF, 0x0)

# clkgrp1_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp1_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp1_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp1_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp1_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0xD0, 0x1)

# clkgrp1_div2_cfg1_en[0:0] = 0x1
# clkgrp1_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp1_div2_cfg2_startmode[3:2] = 0x3
# clkgrp1_div2_cfg1_rev[4:4] = 0x1
# clkgrp1_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp1_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp1_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0xD2, 0xFD)

# clkgrp1_div2_cfg12_divrat_lsb[7:0] = 0xFA
dut.write(0xD3, 0xFA)

# clkgrp1_div2_cfg12_divrat_msb[3:0] = 0x0
dut.write(0xD4, 0x0)

# clkgrp1_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0xD5, 0x0)

# clkgrp1_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xD6, 0x0)

# clkgrp1_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xD7, 0x0)

# clkgrp1_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0xD8, 0x0)

# clkgrp1_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp1_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0xD9, 0x0)

# clkgrp1_div2_cfg5_drvr_res[1:0] = 0x1
# clkgrp1_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp1_div2_cfg5_drvr_mode[4:3] = 0x0
# clkgrp1_div2_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp1_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0xDA, 0x1)

# clkgrp2_div1_cfg1_en[0:0] = 0x0
# clkgrp2_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp2_div1_cfg2_startmode[3:2] = 0x3
# clkgrp2_div1_cfg1_rev[4:4] = 0x1
# clkgrp2_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp2_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp2_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0xDC, 0xFE)

# clkgrp2_div1_cfg12_divrat_lsb[7:0] = 0x8
dut.write(0xDD, 0x8)

# clkgrp2_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0xDE, 0x0)

# clkgrp2_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0xDF, 0x0)

# clkgrp2_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xE0, 0x0)

# clkgrp2_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xE1, 0x0)

# clkgrp2_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0xE2, 0x0)

# clkgrp2_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp2_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0xE3, 0x0)

# clkgrp2_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp2_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp2_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp2_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp2_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0xE4, 0x1)

# clkgrp2_div2_cfg1_en[0:0] = 0x1
# clkgrp2_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp2_div2_cfg2_startmode[3:2] = 0x3
# clkgrp2_div2_cfg1_rev[4:4] = 0x1
# clkgrp2_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp2_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp2_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0xE6, 0xFD)

# clkgrp2_div2_cfg12_divrat_lsb[7:0] = 0xFA
dut.write(0xE7, 0xFA)

# clkgrp2_div2_cfg12_divrat_msb[3:0] = 0x0
dut.write(0xE8, 0x0)

# clkgrp2_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0xE9, 0x0)

# clkgrp2_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xEA, 0x0)

# clkgrp2_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xEB, 0x0)

# clkgrp2_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0xEC, 0x0)

# clkgrp2_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp2_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0xED, 0x0)

# clkgrp2_div2_cfg5_drvr_res[1:0] = 0x1
# clkgrp2_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp2_div2_cfg5_drvr_mode[4:3] = 0x0
# clkgrp2_div2_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp2_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0xEE, 0x1)

# clkgrp3_div1_cfg1_en[0:0] = 0x0
# clkgrp3_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp3_div1_cfg2_startmode[3:2] = 0x0
# clkgrp3_div1_cfg1_rev[4:4] = 0x1
# clkgrp3_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp3_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp3_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0xF0, 0xF2)

# clkgrp3_div1_cfg12_divrat_lsb[7:0] = 0x2
dut.write(0xF1, 0x2)

# clkgrp3_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0xF2, 0x0)

# clkgrp3_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0xF3, 0x0)

# clkgrp3_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xF4, 0x0)

# clkgrp3_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xF5, 0x0)

# clkgrp3_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0xF6, 0x0)

# clkgrp3_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp3_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0xF7, 0x0)

# clkgrp3_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp3_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp3_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp3_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp3_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0xF8, 0x1)

# clkgrp3_div2_cfg1_en[0:0] = 0x0
# clkgrp3_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp3_div2_cfg2_startmode[3:2] = 0x3
# clkgrp3_div2_cfg1_rev[4:4] = 0x1
# clkgrp3_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp3_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp3_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0xFA, 0xFC)

# clkgrp3_div2_cfg12_divrat_lsb[7:0] = 0x0
dut.write(0xFB, 0x0)

# clkgrp3_div2_cfg12_divrat_msb[3:0] = 0x1
dut.write(0xFC, 0x1)

# clkgrp3_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0xFD, 0x0)

# clkgrp3_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0xFE, 0x0)

# clkgrp3_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0xFF, 0x0)

# clkgrp3_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x100, 0x0)

# clkgrp3_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp3_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x101, 0x0)

# clkgrp3_div2_cfg5_drvr_res[1:0] = 0x0
# clkgrp3_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp3_div2_cfg5_drvr_mode[4:3] = 0x2
# clkgrp3_div2_cfg_outbuf_dyn[5:5] = 0x1
# clkgrp3_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x102, 0x30)

# clkgrp4_div1_cfg1_en[0:0] = 0x0
# clkgrp4_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp4_div1_cfg2_startmode[3:2] = 0x0
# clkgrp4_div1_cfg1_rev[4:4] = 0x1
# clkgrp4_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp4_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp4_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0x104, 0xF2)

# clkgrp4_div1_cfg12_divrat_lsb[7:0] = 0x2
dut.write(0x105, 0x2)

# clkgrp4_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0x106, 0x0)

# clkgrp4_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0x107, 0x0)

# clkgrp4_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x108, 0x0)

# clkgrp4_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x109, 0x0)

# clkgrp4_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x10A, 0x0)

# clkgrp4_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp4_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x10B, 0x0)

# clkgrp4_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp4_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp4_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp4_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp4_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0x10C, 0x1)

# clkgrp4_div2_cfg1_en[0:0] = 0x0
# clkgrp4_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp4_div2_cfg2_startmode[3:2] = 0x3
# clkgrp4_div2_cfg1_rev[4:4] = 0x1
# clkgrp4_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp4_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp4_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0x10E, 0xFC)

# clkgrp4_div2_cfg12_divrat_lsb[7:0] = 0x0
dut.write(0x10F, 0x0)

# clkgrp4_div2_cfg12_divrat_msb[3:0] = 0x1
dut.write(0x110, 0x1)

# clkgrp4_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0x111, 0x0)

# clkgrp4_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x112, 0x0)

# clkgrp4_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x113, 0x0)

# clkgrp4_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x114, 0x0)

# clkgrp4_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp4_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x115, 0x0)

# clkgrp4_div2_cfg5_drvr_res[1:0] = 0x0
# clkgrp4_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp4_div2_cfg5_drvr_mode[4:3] = 0x2
# clkgrp4_div2_cfg_outbuf_dyn[5:5] = 0x1
# clkgrp4_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x116, 0x30)

# clkgrp5_div1_cfg1_en[0:0] = 0x0
# clkgrp5_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp5_div1_cfg2_startmode[3:2] = 0x0
# clkgrp5_div1_cfg1_rev[4:4] = 0x1
# clkgrp5_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp5_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp5_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0x118, 0xF2)

# clkgrp5_div1_cfg12_divrat_lsb[7:0] = 0x2
dut.write(0x119, 0x2)

# clkgrp5_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0x11A, 0x0)

# clkgrp5_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0x11B, 0x0)

# clkgrp5_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x11C, 0x0)

# clkgrp5_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x11D, 0x0)

# clkgrp5_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x11E, 0x0)

# clkgrp5_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp5_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x11F, 0x0)

# clkgrp5_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp5_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp5_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp5_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp5_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0x120, 0x1)

# clkgrp5_div2_cfg1_en[0:0] = 0x0
# clkgrp5_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp5_div2_cfg2_startmode[3:2] = 0x3
# clkgrp5_div2_cfg1_rev[4:4] = 0x1
# clkgrp5_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp5_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp5_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0x122, 0xFC)

# clkgrp5_div2_cfg12_divrat_lsb[7:0] = 0x0
dut.write(0x123, 0x0)

# clkgrp5_div2_cfg12_divrat_msb[3:0] = 0x1
dut.write(0x124, 0x1)

# clkgrp5_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0x125, 0x0)

# clkgrp5_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x126, 0x0)

# clkgrp5_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x127, 0x0)

# clkgrp5_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x128, 0x0)

# clkgrp5_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp5_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x129, 0x0)

# clkgrp5_div2_cfg5_drvr_res[1:0] = 0x0
# clkgrp5_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp5_div2_cfg5_drvr_mode[4:3] = 0x2
# clkgrp5_div2_cfg_outbuf_dyn[5:5] = 0x1
# clkgrp5_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x12A, 0x30)

# clkgrp6_div1_cfg1_en[0:0] = 0x0
# clkgrp6_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp6_div1_cfg2_startmode[3:2] = 0x0
# clkgrp6_div1_cfg1_rev[4:4] = 0x1
# clkgrp6_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp6_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp6_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0x12C, 0xF2)

# clkgrp6_div1_cfg12_divrat_lsb[7:0] = 0x2
dut.write(0x12D, 0x2)

# clkgrp6_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0x12E, 0x0)

# clkgrp6_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0x12F, 0x0)

# clkgrp6_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x130, 0x0)

# clkgrp6_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x131, 0x0)

# clkgrp6_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x132, 0x0)

# clkgrp6_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp6_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x133, 0x0)

# clkgrp6_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp6_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp6_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp6_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp6_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0x134, 0x1)

# clkgrp6_div2_cfg1_en[0:0] = 0x0
# clkgrp6_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp6_div2_cfg2_startmode[3:2] = 0x3
# clkgrp6_div2_cfg1_rev[4:4] = 0x1
# clkgrp6_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp6_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp6_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0x136, 0xFC)

# clkgrp6_div2_cfg12_divrat_lsb[7:0] = 0x0
dut.write(0x137, 0x0)

# clkgrp6_div2_cfg12_divrat_msb[3:0] = 0x1
dut.write(0x138, 0x1)

# clkgrp6_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0x139, 0x0)

# clkgrp6_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x13A, 0x0)

# clkgrp6_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x13B, 0x0)

# clkgrp6_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x13C, 0x0)

# clkgrp6_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp6_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x13D, 0x0)

# clkgrp6_div2_cfg5_drvr_res[1:0] = 0x0
# clkgrp6_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp6_div2_cfg5_drvr_mode[4:3] = 0x2
# clkgrp6_div2_cfg_outbuf_dyn[5:5] = 0x1
# clkgrp6_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x13E, 0x30)

# clkgrp7_div1_cfg1_en[0:0] = 0x0
# clkgrp7_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp7_div1_cfg2_startmode[3:2] = 0x0
# clkgrp7_div1_cfg1_rev[4:4] = 0x1
# clkgrp7_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp7_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp7_div1_cfg1_hi_perf[7:7] = 0x1
dut.write(0x140, 0xF2)

# clkgrp7_div1_cfg12_divrat_lsb[7:0] = 0x10
dut.write(0x141, 0x10)

# clkgrp7_div1_cfg12_divrat_msb[3:0] = 0x0
dut.write(0x142, 0x0)

# clkgrp7_div1_cfg5_fine_delay[4:0] = 0x0
dut.write(0x143, 0x0)

# clkgrp7_div1_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x144, 0x0)

# clkgrp7_div1_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x145, 0x0)

# clkgrp7_div1_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x146, 0x0)

# clkgrp7_div1_cfg2_sel_outmux[1:0] = 0x0
# clkgrp7_div1_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x147, 0x0)

# clkgrp7_div1_cfg5_drvr_res[1:0] = 0x1
# clkgrp7_div1_cfg5_drvr_spare[2:2] = 0x0
# clkgrp7_div1_cfg5_drvr_mode[4:3] = 0x0
# clkgrp7_div1_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp7_div1_cfg2_mutesel[7:6] = 0x0
dut.write(0x148, 0x1)

# clkgrp7_div2_cfg1_en[0:0] = 0x0
# clkgrp7_div2_cfg1_phdelta_mslip[1:1] = 0x0
# clkgrp7_div2_cfg2_startmode[3:2] = 0x3
# clkgrp7_div2_cfg1_rev[4:4] = 0x1
# clkgrp7_div2_cfg1_slipmask[5:5] = 0x1
# clkgrp7_div2_cfg1_reseedmask[6:6] = 0x1
# clkgrp7_div2_cfg1_hi_perf[7:7] = 0x1
dut.write(0x14A, 0xFC)

# clkgrp7_div2_cfg12_divrat_lsb[7:0] = 0x0
dut.write(0x14B, 0x0)

# clkgrp7_div2_cfg12_divrat_msb[3:0] = 0x1
dut.write(0x14C, 0x1)

# clkgrp7_div2_cfg5_fine_delay[4:0] = 0x0
dut.write(0x14D, 0x0)

# clkgrp7_div2_cfg5_sel_coarse_delay[4:0] = 0x0
dut.write(0x14E, 0x0)

# clkgrp7_div2_cfg12_mslip_lsb[7:0] = 0x0
dut.write(0x14F, 0x0)

# clkgrp7_div2_cfg12_mslip_msb[3:0] = 0x0
dut.write(0x150, 0x0)

# clkgrp7_div2_cfg2_sel_outmux[1:0] = 0x0
# clkgrp7_div2_cfg1_drvr_sel_testclk[2:2] = 0x0
dut.write(0x151, 0x0)

# clkgrp7_div2_cfg5_drvr_res[1:0] = 0x0
# clkgrp7_div2_cfg5_drvr_spare[2:2] = 0x0
# clkgrp7_div2_cfg5_drvr_mode[4:3] = 0x2
# clkgrp7_div2_cfg_outbuf_dyn[5:5] = 0x1
# clkgrp7_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x152, 0x30)

Parents
  • Hi 

    Achieving deterministic phase relation is possible for your configuration. The deterministic latency can be calculated as follows: 

    RFSYNC input is sampled with an input clock at the rising edge. The synchronization (or SYSREF generation) process starts with the detection of RFSYNC falling edge.

    How much are latency values different from each power-up / reseed? 

    I have two observations about your configuration. 

    1 - providing a continuous signal to RFSYNC input is not a good approach. This might create problems with synchronization FSM depending on the frequency. We recommend a single-pulse RFSYNC signal for synchronization. 

    2 - I saw that your divider values 4, 8, and 250 while the SYSREF timer value is 250. We recommend that every divider value should be an integer sub-multiple of the SYSREF timer. Can you repeat your test by changing your divider values to 4, 8, 256, and sysref timer value to 256.

    Thanks,

    Emrecan

  • 1) Unfortunately I don't have the option to provide a single-pulse RFSYNC signal, can you provide more information about the frequency constrains?

    2) I was switching off the sensitivity to RFSYNC (RF reseeder enable, reg 0x3[5]) from the GUI, so depending on what part of the duty cycle was there at the moment of the disabling the synchronization was happening at the correct rising edge or randomly. My hypothesis is that controlling better the instant at which I turn the reseeding off will solve my issues.

  • About point 2)
    With polarity set to "+" a rising edge will reset sysref timer and dividers and a falling edge will start again all the components, so sysref and the output phases will be aligned to the falling edge is I understand correctly.
    Let's say that "RF reseeder enable" is on, every rising edge initiates the sync and every falling edge will start the internal timer. Then I decide to turn the RF reseeder off and start a local generation of sysref, what happens if I disable it after a rising edge but before a falling edge? Will this create an "artificial falling edge" and ruin the synchronization?

    And in that case, is there a way to safely disable the sensitivity to the external RF signal but maintaining deterministic phase relation between the internal and external sysref?

    Thank you

  • Hi,  

    I have one correction to your comment. Since the RFSYNC signal is sampled by the rising edge of the input clock, the first rising edge of the input clock after the RFSYNC trigger resets synchronization dividers, not the RFSYNC signals itself. 

    In your case, if synchronization is done once, there is no need for additional synchronization as long as channels are not disabled or divider values are not changed. HMC7043 maintains synchronization.  

    As long as you use the Pulsor request to generate local SYSREF after external synchronization,  deterministic phase relation with the external SYSREF signal will be maintained. However, if a Reseed Request is used to generate a SYSREF signal, a deterministic phase relation might be lost as the Reseed request also resets the SYSREF FSM. 

    Thanks,

    Emrecan

Reply
  • Hi,  

    I have one correction to your comment. Since the RFSYNC signal is sampled by the rising edge of the input clock, the first rising edge of the input clock after the RFSYNC trigger resets synchronization dividers, not the RFSYNC signals itself. 

    In your case, if synchronization is done once, there is no need for additional synchronization as long as channels are not disabled or divider values are not changed. HMC7043 maintains synchronization.  

    As long as you use the Pulsor request to generate local SYSREF after external synchronization,  deterministic phase relation with the external SYSREF signal will be maintained. However, if a Reseed Request is used to generate a SYSREF signal, a deterministic phase relation might be lost as the Reseed request also resets the SYSREF FSM. 

    Thanks,

    Emrecan

Children
  • Thanks for the clarification. My question arised from the fact that I didn't find an easy way to do the first synchronization. The obvious solution would just be to gate the incoming free running sysref to a single pulse, but I wanted to make sure that I could not accomplish it with some other mechanisms.

    As a result form this thread I understand that there is no way to synchronize the HMC7044 with a continuous SYSREF with my configuration, I'll add a component to gate my signal.

    Thanks a bunch