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HMC7043 Recommended for New Designs
The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution...
Datasheet
HMC7043 on Analog.com

Query on phase offset of SYSREF output channel configured as pulse generator.

Merlyn

on Apr 16, 2024

Category: Datasheet/Specs

Product Number: HMC7043

Hi,

I have a query w.r.t HMC7043 clock distributor.
Pg 20 of datasheet (www.analog.com/.../HMC7043.pdf) states the following to avoid creating a runt pulse:

"The situation is avoided by never applying phase offset more
than (50% − 8) clock input cycles to an output channel
configured as a pulse generator."

Can someone help me understand what does (50% - 8) clock input cycle mean? Also how we can calculate the above value (here is 8 being subtracted from 50 % ?) . How can we verify that phase offset < (50% -8) clock input cycles.

Thanks,

Merlyn

0 emrecangidik

4 months ago
Hi Merylin,

Thanks for bringing this to our attention. There seems to be some confusing information in the section on Page 20 of the datasheet. I took note of that and will add clarification for the next revision.

50% means that half of the output clock period. The "8" is unitless because it refers to the flip-flop-based digital delay value of the channel.

For example, assume the clock input frequency is 2GHz and the channel divider value is 20. The step size of the flip-flop-based digital delay becomes 250ps (input clock period / 2). the output frequency of the channel is 100MHz and the period is 10ns.

To avoid runt pulses on this channel, the digital delay value (phase offset) should be kept smaller than 5ns - 8 * 250ps (3ns). So, the total flip-flop-based digital delay value shouldn't exceed 12 (3ns/250ps )

I hope it is more clear now. Please let me know if there is something open.

Thanks,

Emrecan
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