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Variable clock input

Category: Datasheet/Specs
Product Number: AD9102

I have read that there is no minimum SRAM clock specified for the AD9102, my question is whether it is also possible to use a variable clock input frequency? My use case is a DC ramp with constant values in between and I want to save RAM space for the time the signal remains constant.

Top Replies

    •  Analog Employees 
    Apr 4, 2024 in reply to HeinerB +2 verified

    Hi  ,

    Thank you for providing your target waveform. It's unusual to have a section where you are not providing a clock. As mentioned, that section without a clock edge will have no output in the…

  • Hi  ,

    Thank you for your interest in AD9102. By variable clock input frequency, do you mean that you will be generating the DC ramp while the DAC sampling frequency is changing? 

    Regards,
    Marco

  • Yes, I would like to have a pre defined ramp stored at the SRAM. I would like to clock the first sample with a specific value at time 0. After that i would like to wait (delay the clkp/clkn) for e.g. 100 µs and than I would like to sample the rest of the SRAM data points with a frequency about 30MHz. I have an FPGA which will generate the clkp/clkn signal.

    Thanks for you reply,

    Heiner

  • I believe this should be doable so long as the resulting number of DAC points required to generate the DC ramp at any given time is within 4096 SRAM addresses. However, for the time you are waiting (i.e. delaying CLKP/CLKN), you won't have any output since the DAC is not able to sample any data without a clock. In other words, it will go back to 0 (midscale), not stay at a constant value. What is the starting frequency in which you will sample the first point? 

    Best regards,
    Marco

  • I've made a small picture to clarify a bit more, see below

    This pattern will be repeated several times. the period time of the clock will be ~33ns, the first pulse @ address0 is panned to be 33ns/2. The time between address 0 -> 1 is about 100µs. It is also possible to expand the fist pulse

  • Hi  ,

    Thank you for providing your target waveform. It's unusual to have a section where you are not providing a clock. As mentioned, that section without a clock edge will have no output in the DAC, it will not stay at the value at SRAM address 0. You need to have a clock in order to sample the SRAM data. 

    What you can do is utilize the Start delay (Register 0x52) feature in AD9102. The Start delay is the delay between the start of each pattern period and the start of the waveform. The value at the beginning of the start delay will be the starting value of the generated waveform and will remain at this value until the Start delay ends. In this way, the value at SRAM address 0 will remain at the DC constant (for the duration of the start delay) and the DAC receives a continuous clock signal. 

    You can simply store in SRAM the ramp-down waveform (blue section) illustrated below. Then, the pattern period must be equal to the Start delay value plus the duration of the SRAM waveform in order to have a repeating pattern. The pattern period will depend on your DAC sampling frequency. Please refer to page 21-22 of the datasheet.

    Best regards,
    Marco

  • Thank you, I think this will work.

    Regards,

    Heiner