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about HMC7044 Multi-chips synchronization

Category: Hardware

Now, I have 1 HMC7044 master device and 4 HMC7044 slaver devices. The master device outputs 4 pairs of REFCLK(DC coupled, LVPECL) and RFSYNC(DC coupled, LVPECL) clocks to the slaver devices. The clock output from the master device is highly synchronized, but the phase between the clocks output from the slaver device is uncertain. My HMC7044 slaver devices is configured to clock distributor mode. How can I use RFSYNC to synchronize the output clocks of four slaver devices.

  • Hi Lulolong, 

    Let's call the first HMC7044 Stage 1 and the others Stage 2. 

    You already determined the output mode. Therefore, I assume you handled the input terminations and output buffer mode selections. If not, you must set the external clock input and RFSYNC input of stage 2 for LVPECL termination. Outputs of Stage 1 should be set as LVPECL buffer mode.  

    To synchronize the multiple clock distributor part, first, you need to synchronize Stage 1 and then generate a synchronization pulse to the next stages from Stage 1.

    The steps are as follows,

    1- Stage 1: Set the correct output mode for Stage 1 outputs. Single pulse generation (Dynamic) for RFSYNC, continuous signal generation (Asynchronous) for REFCLCK. 

    2- Stage 1: Set the SYSREF Timer value the same as the dynamic channels divider values. This will provide a single pulse at the dynamic outputs.  (Register 0x5C and 0x5D should be same with divider values of channels in the dynamic mode)

    3- Stage 1: Set pulse Generator mode selection (Register 0x5A[2:0] = b'001) to signal pulse mode.   

    4- Stage 2: Set the correct input termination for LVPECL for CLKIN0 (RFSYNC) and CLKIN1 (REFCLK)

    5- Stage 2: Enable RFSYNC input and RF Reseeder so Stage 2 parts are susceptible to triggers at RFSYNC input. Register 0x03[5] = 1, Register 0x05[5] = 1. 

    6 - Stage 2: In your case, set stage 2 parts for fan-out mode operation. Steps are in (1) HMC7044 - Q&A - Clock and Timing - EngineerZone (

    7- Stage 1; provides a digital delay for pulse generation channels as much as half of the continuous channels divider value. This is needed to prevent any setup/hold time violations

    8- Stage 1: synchronize the output channels by issuing a Reseed request. 

    9-Stage 1: Issue a pulsor request to provide a pulse signal for stage 2 synchronization. 

    After these steps, 4 HMC7044s at stage 2 should be synchronized. If there is a cable mismatch between different stages, you can mitigate these mismatches at the first stage, so external clocks to stage 2 parts can arrive at the same time.  



  • HI, Emrecan

     I find a question. In step 9, I send a GPIO pulse to master HMC7044 used for generate RFSYNC, but the stage generate a SYSREF pulse after RFSYNC. Is the phenomenon normal?