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Impact of unconnected LTC6952 charge pump pin on JESD link behaviour

Category: Hardware

Hello all,

We are working on a custom board consisting of JESD204B (subclass1) link between Xilinx Kintex Ultrascale and AD9162.

the hardware design is based on example found in LTC6952 datasheet:

but in our hardware design, CP pin of LTC6952 is unconnected

my qyestion is: does the unconnected CP pin impact the subclass1 JESD link stability (in terms of phase alignment between SYSREFs and device clocks as example) ? and how to deal with that to ensure the stability of JESD204b subclass1 ?



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