Impact of unconnected LTC6952 charge pump pin on JESD link behaviour

Question

Hello all, 
 
 We are working on a custom board consisting of JESD204B (subclass1) link between Xilinx Kintex Ultrascale and AD9162. 
 the hardware design is based on example found in LTC6952 datasheet:

but in our hardware design, CP pin of LTC6952 is unconnected 
 my qyestion is: does the unconnected CP pin impact the subclass1 JESD link stability (in terms of phase alignment between SYSREFs and device clocks as example) ? and how to deal with that to ensure the stability of JESD204b subclass1 ? 
 
 Thanks 
 A.B.

ChrisPearson · Accepted Answer

Hi all, 
 For awareness, Both the LTC6952 and LTC6955 had moved to lifetime buy status. ADI_PDN_23_0089_Rev_A_Form.pdf (analog.com) . 
 If the External source is frequency locked, then this maybe ok to do. Another option is the HMC7043 has a /2 on its input that supports up to 6GHz. this would work if the external source does not go above 6GHz (and is locked to something). The HMC7043 is recommended for new designs.)

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Impact of unconnected LTC6952 charge pump pin on JESD link behaviour