AD9528 reference input noise sensitivity and behaviour with no input signal

Hi,

The recommendation is to always apply differential clocks that have the minimum peak to peak voltages given in the specification rows above the input noise sensitivity entry:

This will make the AD9528 to function with the best performance. Then, imagine the reference clock shuts down to 0V, AD9528 sees the reference clock at PFD input is missing for 2 PFD cycled and as a consequence, the AD9528 decides the reference is missing. One needs to make sure the noise on the reference is always smaller than 5mV typ in order for the AD9528 to continue to consider that reference is missing. Otherwise, the AD9528 may consider the clocks as "correct" and try to lock the PLL1 onto it. Use ac coupled clocks to overcome this specification.

"As the P and N pin voltages are the same, will the input buffer oscillate or be sensitive to external noise? "

No, see explanation above.

"If so, should we add a fail-safe circuit to force P and N to have an offset"

There is no need for such additional resistors because the clock is ac coupled.

Petre

Thanks Petre, thanks for getting back so promptly.  We'll AC couple the clock and try to ensure that any noise picked up on the differential reference traces or at the AD9528 reference pins is always <5mV. 

Thanks Petre, thanks for getting back so promptly.  We'll AC couple the clock and try to ensure that any noise picked up on the differential reference traces or at the AD9528 reference pins is always <5mV.