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AD9528 reference input noise sensitivity and behaviour with no input signal

Category: Datasheet/Specs
Product Number: AD9528

Hello.

Please could you let me know what the 5mV input noise sensitivity means on page 5 of the datasheet?

Also, we are planning to use an AC coupled clock into the reference pins, as shown in the picture below from page 22 of the datasheet. If the clock signal is not present then the P and N pins will presumably sit at the internally generated common mode voltage. As the P and N pin voltages are the same, will the input buffer oscillate or be sensitive to external noise? If so, should we add a fail-safe circuit to force P and N to have an offset, such as the "External-Biasing Fail-Safe Circuit" described in www.analog.com/.../understanding-lvds-failsafe-circuits.html

                     AC coupled reference input

Thank you for the assistance.



Typo
[edited by: daedalus at 5:16 PM (GMT -5) on 2 Feb 2024]
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  • Hi,

    The recommendation is to always apply differential clocks that have the minimum peak to peak voltages given in the specification rows above the input noise sensitivity entry:

    This will make the AD9528 to function with the best performance. Then, imagine the reference clock shuts down to 0V, AD9528 sees the reference clock at PFD input is missing for 2 PFD cycled and as a consequence, the AD9528 decides the reference is missing. One needs to make sure the noise on the reference is always smaller than 5mV typ in order for the AD9528 to continue to consider that reference is missing. Otherwise, the AD9528 may consider the clocks as "correct" and try to lock the PLL1 onto it. Use ac coupled clocks to overcome this specification.

    "As the P and N pin voltages are the same, will the input buffer oscillate or be sensitive to external noise"

    No, see explanation above.

    "If so, should we add a fail-safe circuit to force P and N to have an offset"

    There is no need for such additional resistors because the clock is ac coupled.

    Petre

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  • Hi,

    The recommendation is to always apply differential clocks that have the minimum peak to peak voltages given in the specification rows above the input noise sensitivity entry:

    This will make the AD9528 to function with the best performance. Then, imagine the reference clock shuts down to 0V, AD9528 sees the reference clock at PFD input is missing for 2 PFD cycled and as a consequence, the AD9528 decides the reference is missing. One needs to make sure the noise on the reference is always smaller than 5mV typ in order for the AD9528 to continue to consider that reference is missing. Otherwise, the AD9528 may consider the clocks as "correct" and try to lock the PLL1 onto it. Use ac coupled clocks to overcome this specification.

    "As the P and N pin voltages are the same, will the input buffer oscillate or be sensitive to external noise"

    No, see explanation above.

    "If so, should we add a fail-safe circuit to force P and N to have an offset"

    There is no need for such additional resistors because the clock is ac coupled.

    Petre

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