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AD9522-1 Recommended for New Designs
The AD9522-11 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip...
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AD9522-1 on Analog.com

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PLL of AD9522-1 does not lock and its output stops after some time

    
		

			

									
					    Fujimoto
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 1, 2024 
				
			
			
		
    
		
     
				
		
    
		    		    
		    
		    		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  AD9522-1  
    
    		        		    		    	
			
    We designed our board with AD9522-1 and have two problems with the board.
    

    

    The first one is PLL seems not to be locked on some boards we produced.
    

    

    Another one is clock output stops suddenly after some time despite PLL is locked.
    

    PLL of these boards is locked just after powered on, but the clock output stops after some time has passed. How long clock output is alive depends on the boards.
    

    

    Board design and register settings are the same for all of the board we made, and PLL settings with the internal VCO used are following.
    

    

    REF1: 27MHz
    

    PDF: 100kHz
    

    R divider: 270d
    

    N divider; 23760 (N counter: 32d, B counter: 742d, A counter: 16d)
    

    Loop filter: the same values of Figure 43 of the datasheet
    

    Output clock: single end CMOS 74.25MHz
    

    

    

    We have investigated the first problem and we have found
    

      

    • DLD from DL pin shows unlocked
      • 

    • R and N divider from STATUS pin run at 100kHz and each pulse width is 37ns and 13ns respectively
      • 

    • No PFD up pulse and PFD down pulse with 50ns width at 100kHz    
      • 

    

    

    Regarding the second problem, it has been found
    

      

    • Output clock frequency and duty varies and before it stops. REF1 still runs at 27MHz when the output clock stops
      • 

    • Stop clock is likely to happens as the board is warmed up
      • 

    

    

    

    We are not sure these two problems caused by the same issue but they seems to be related to PLL.
    

    It would be very appreciated if you could give us how to debug them.
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Clock Generation Devices
                
                                                    
                 Clock Generation and Distribution
                
                                                    
                 hardware
                
                                                    
                 clock and timing
                
                                                    
                 AD9522-1
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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													+1
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 2, 2024 1:50 PM
            

            
					
      
	
      

		
		
      
					
      HI,
      

      next time, please send the stp file you created on the AD9522-1 evaluation software. We always recommend to use the evaluation software to create the desired configuration, even if you do not use an evaluation board to test that configuration. Have you tried this configuration on an evaluation board before using it on your own board?
      

      To me, it seems the configuration should work, although I do not really like using R and N dividers so high. I created two configurations: one that uses a R divider=2, N=176, Prescaler=16/17 DM mode and another one that uses R divider=4, N=352, Prescaler=32/33 DM mode (attached).
      

      



      
    
      
        Fullscreen
        AD9522_1_setup_petre.stp.txt
        Download
    
      
    
      "AD9522 Setup File"
"Rev.","0.0.1"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00000000","00"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","01111100","7C"
"0011","00000010","02"
"0012","00000000","00"
"0013","00000000","00"
"0014","00001011","0B"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","10000000","80"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","11100010","E2"
"00F1","01100010","62"
"00F2","01100010","62"
"00F3","01100010","62"
"00F4","01100010","62"
"00F5","01100010","62"
"00F6","01100010","62"
"00F7","01100010","62"
"00F8","01100010","62"
"00F9","01100010","62"
"00FA","01100010","62"
"00FB","01100010","62"
"00FC","00000000","00"
"00FD","00000000","00"
"00FE","00000000","00"
"0190","01110111","77"
"0191","00000000","00"
"0192","00000000","00"
"0193","00110011","33"
"0194","00000000","00"
"0195","00000000","00"
"0196","00010001","11"
"0197","00000000","00"
"0198","00000000","00"
"0199","00000000","00"
"019A","00000000","00"
"019B","00000000","00"
"019C","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00001011","0B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000001","01"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"
"","",""
"Other Settings..."
"REF 1:",27
"REF 2:",30.72
"VCO:",2376
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1
""
"CheckSum Values"
"8-Bit Device Checksum (uses R0x000 to R0x232): ","0x6EC"
"8-Bit Data Pattern Checksum (all regs): ","0xB3E"
"16-Bit Device Checksum (uses R0x000 to R0x232): ","0x306E9"
"16-Bit Data Pattern Checksum (all regs): ","0x570D3"

      

      


      

      



      
    
      
        Fullscreen
        AD9522_1_setup_petre2.stp.txt
        Download
    
      
    
      "AD9522 Setup File"
"Rev.","0.0.1"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00000000","00"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","01111100","7C"
"0011","00000100","04"
"0012","00000000","00"
"0013","00000000","00"
"0014","00001011","0B"
"0015","00000000","00"
"0016","00000110","06"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","10000000","80"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","11100010","E2"
"00F1","01100010","62"
"00F2","01100010","62"
"00F3","01100010","62"
"00F4","01100010","62"
"00F5","01100010","62"
"00F6","01100010","62"
"00F7","01100010","62"
"00F8","01100010","62"
"00F9","01100010","62"
"00FA","01100010","62"
"00FB","01100010","62"
"00FC","00000000","00"
"00FD","00000000","00"
"00FE","00000000","00"
"0190","01110111","77"
"0191","00000000","00"
"0192","00000000","00"
"0193","00110011","33"
"0194","00000000","00"
"0195","00000000","00"
"0196","00010001","11"
"0197","00000000","00"
"0198","00000000","00"
"0199","00000000","00"
"019A","00000000","00"
"019B","00000000","00"
"019C","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00001011","0B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000001","01"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"
"","",""
"Other Settings..."
"REF 1:",27
"REF 2:",30.72
"VCO:",2376
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1
""
"CheckSum Values"
"8-Bit Device Checksum (uses R0x000 to R0x232): ","0x6EF"
"8-Bit Data Pattern Checksum (all regs): ","0xB41"
"16-Bit Device Checksum (uses R0x000 to R0x232): ","0x308EA"
"16-Bit Data Pattern Checksum (all regs): ","0x572D4"

      

      


      

      "The first one is PLL seems not to be locked on some boards we produced."
      

      

      Please change the REFA clock source with a signal generator and see if the problem continues.
      

      "PLL of these boards is locked just after powered on, but the clock output stops after some time has passed. How long clock output is alive depends on the boards."
      

      

      This is weird. Please send me the schematic of the AD9522-1 for me to take a look.
      

      I do not have an AD9522-1 evaluation board to test the configurations I send you, but I am pretty sure they should work. I have ordered one anyway.
      

      Petre
      

      

      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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