We designed our board with AD9522-1 and have two problems with the board.
The first one is PLL seems not to be locked on some boards we produced.
Another one is clock output stops suddenly after some time despite PLL is locked.
PLL of these boards is locked just after powered on, but the clock output stops after some time has passed. How long clock output is alive depends on the boards.
Board design and register settings are the same for all of the board we made, and PLL settings with the internal VCO used are following.
REF1: 27MHz
PDF: 100kHz
R divider: 270d
N divider; 23760 (N counter: 32d, B counter: 742d, A counter: 16d)
Loop filter: the same values of Figure 43 of the datasheet
Output clock: single end CMOS 74.25MHz
We have investigated the first problem and we have found
- DLD from DL pin shows unlocked
- R and N divider from STATUS pin run at 100kHz and each pulse width is 37ns and 13ns respectively
- No PFD up pulse and PFD down pulse with 50ns width at 100kHz
Regarding the second problem, it has been found
- Output clock frequency and duty varies and before it stops. REF1 still runs at 27MHz when the output clock stops
- Stop clock is likely to happens as the board is warmed up
We are not sure these two problems caused by the same issue but they seems to be related to PLL.
It would be very appreciated if you could give us how to debug them.