I have a question. I have configured AD9528 as follows. I found that when Ref A does not have a clock input, 9528 will still output the set clock normally. Is the internal VCXO clock locked at this time? Will 9528 automatically use Ref A's clock input as a reference when I input the preset clock signal into Ref A after the clock outputs normally for a period of time?
HI,
your AD9528 generates an output because I believe the PLL2 has locked. You should verify PLL2 has locked by reading bit 1 of register 0x508.
You say that after AD9528 outputs a clock, then you can input a reference clock at REFA. Please look at the initialization process presented at page 41 in rev F data sheet. It states the reference clock must be applied after power up, not after PLL2 locked:
If you do not apply any reference after power up and apply it after PLL2 has locked, the AD9528 should automatically select REFA. See page 26 in rev F data sheet.
REFB is not enabled in your configuration anyway.
Because REFB is not enabled, I recommend manually select REFA as the active reference by setting bits 2:0 in register 0x010A to 010.
"How to determine whether the reference clock of Refa is in effect"
Monitor bit 2 in register 0x0509. Note that if you select REFA manually, this does not function.
"or the VCXO clock that has been locked earlier?"
The VCXO status may be found in bit 5 in register 0x0508.
Generally, see registers 0x508 and 0x509 for various status bits or use STATUS0 and STATUS1 pins to output various status bits.
I looked over the stp file. I recommend using Ra=2, N1=2 instead of Ra=4, N1=4 because this will reduce a little the noise of the PLL1. The configuration is OK in any case.
Petre
