AD9528
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The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
AD9528 on Analog.com
Hi,
We have a custom board with zu11eg running petalinux and xcvr AD9026, where AD9528 Clock chip is tied to spi CSS2. The clock chip is added as a jesd device.
During boot The spi initialization fails with error code -14. If you remove the jesd device declaration, then we don't see the error, but the rest of the jesd topology cannot find ad9528 and therefore do not get initialized. Is there anyone who experienced the same, or point me to the right direction please. Thanks
root@zynqmp-iwg35m:~# dmesg | grep 9528
[ 2.232977] jesd204: created con: id=3, topo=10, link=3, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi_adxcvr@a0080000
[ 2.233006] jesd204: created con: id=4, topo=10, link=0, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi_adxcvr@a0040000
[ 2.233037] jesd204: created con: id=5, topo=10, link=2, /axi/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi_adxcvr@a0000000
[ 5.230237] ad9528 spi0.2: supply vcc not found, using dummy regulator
[ 5.267192] jesd204: /axi/spi@ff040000/ad9528-1@0,jesd204:1,parent=spi0.2: Device isn't a top-device, nor does it belong to topology with top-device
[ 5.280512] ad9528: probe of spi0.2 failed with error -14
device tree entry:
&spi0 {
status = "okay";
num-cs = <3>;
is-decoded-cs = <0>;
#address-cells = <1>;
#size-cells = <0>;
clk0_ad9528: ad9528-1@0 {
compatible = "adi,ad9528";
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2",
"ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6",
"ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10",
"ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
#clock-cells = <1>;
adi,vcxo-freq = <100000000>;
/* adi,osc-diff-rcv-enable; */
/* PLL1 config - not needed */
/* disable both reference inputs
adi,refa-enable;
adi,refa-diff-rcv-e;
adi,refa-r-div = <1>;
adi,osc-in-cmos-neg-inp-enable;
adi,pll1-feedback-div = <10>;
adi,pll1-charge-pump-current-nA = <6000>; */
/* PLL2 config */
adi,pll2-m1-frequency = <1000000000>;
/* This is redundant
adi,pll2-vco-div-m1 = <4>;
adi,pll2-n2-div = <10>; */ /* N / M1 */
adi,pll2-r1-div = <1>;
adi,pll2-charge-pump-current-nA = <806000>;
/* SYSREF config */
adi,sysref-src = <SYSREF_SRC_INTERNAL>;
adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
adi,sysref-k-div = <512>;
adi,sysref-request-enable;
adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;
adi,rpole2 = <RPOLE2_900_OHM>;
adi,rzero = <RZERO_1850_OHM>;
adi,cpole1 = <CPOLE1_16_PF>;
adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
adi,status-mon-pin1-function-select = <7>; /* REFA Correct */
ad9528_0_c0: channel@0 {
reg = <0>;
adi,extended-name = "DEV_CLK_TEST";
adi,driver-mode = <DRIVER_MODE_LVDS>;
adi,divider-phase = <0>;
adi,channel-divider = <4>;
adi,signal-source = <SOURCE_VCO>;
};
ad9528_0_c5: channel@5 {
reg = <5>;
adi,extended-name = "DEV_CLK";
adi,driver-mode = <DRIVER_MODE_LVDS>;
adi,divider-phase = <4>;
adi,channel-divider = <4>;
adi,signal-source = <SOURCE_VCO>;
};
ad9528_0_c7: channel@7 {
reg = <7>;
adi,extended-name = "DEV_SYSREF";
adi,driver-mode = <DRIVER_MODE_LVDS>;
adi,divider-phase = <8>;
adi,channel-divider = <8>;
adi,signal-source = <SOURCE_VCO>;
};
ad9528_0_c9: channel@9 {
reg = <9>;
adi,extended-name = "FPGA_SYSREF";
adi,driver-mode = <DRIVER_MODE_LVDS>;
adi,divider-phase = <8>;
adi,channel-divider = <8>;
adi,signal-source = <SOURCE_SYSREF_VCO>;
};
ad9528_0_c10: channel@10 {
reg = <10>;
adi,extended-name = "FPGA_REFCLK";
adi,driver-mode = <DRIVER_MODE_LVDS>;
adi,divider-phase = <4>;
adi,channel-divider = <4>;
adi,signal-source = <SOURCE_SYSREF_VCO>;
};
};
};