AD9910 multiple device synchronization: +/- 1 SYNC_CLK random delay in outputs

Hello,

We have designed a custom board with 4 DDS AD9910, and we are trying to synchronize them in order to have coherents 4 output signals.

We have a design which is very close to the figure 53 of the datasheet, and we paid attention to the layout of our board to have matched length traces for clocks, IO_UPDATE and SYNC_IN signals:

The clock generator used is the CDCE62002, and clock buffers LMK1D1216.

I’ve read a lot of documentation concerning the synchronization of the AD9910, and I think that I have a quite good understanding of the feature, but unfortunately we still don’t succeed in a perfect synchronization. The problem is that when we make a global reset of the board several times, sometime the 4 output signals (they are all at the same frequency in order to facilitate the synchronziation validation procedure, =1MHz.) are perfectly aligned, and sometimes, about a delay of 1 or 2 SYNC_CLK perdiod is observe between them; it’s seem to be a quite randomly process.

Here is how we make our configuration setup:

1. Power on the board
2. Configure the clock generator @60MHz
3. Apply a master reset on all the AD9910
4. Configure the AD9910 registers as folow:
   1. The first AD9910 as the master, and the other 3 as slave (by enabling the sync generator/sync receiver in register 0x0A)
   2. REFCLK input divider bypassed (CFR3[15] = 1), and REFCLK PLL bypassed (which is the default value)
   3. Output frequency of 1MHz, in single tone mode
5. Send an IO_UPDATE coincidentally to all the AD9910.

What we observe with an oscilloscope when doing successive resets of the board is:

1. Sometime the 4 outputs @1MHz are perfectly aligned (so a good synchronization between DDS), and sometimes there is a time delay of 1 or 2 SYNC_CLK period between 2 outputs, which is our main problem (because of course what we want if a reset is done is to always have the same delay between the outputs, in other words: synchronization). If no reset of the board is done, the synchronization of the DDS is ok, the time delay between the output never change. So our problem concerns the reset action (or power-Down/power-up of the board), and the non-repetetive results on the DDS outputs.
2. The 60 MHz REF_CLK signals are always well aligned at the input pins of the 4 DDS
3. The IO_UPDATE signals are always well aligned at the input of the 4 DDS
4. The SYNC_CLK signals of the 4 DDS are always well aligned: I assume that it means that the Sync timing validation is ok.

After trying a lot of things we can’t succeed in understanding why sometime a time delay of 1 or 2 SYNC_CLK period appears between 2 outputs, after a reset… may someone have any idea ?

And some auxiliaries question I have:

1. Since we bypass the REFCLK input divider when sending the IO_UPDATE, the SYSCLK et SYNC_CLK frequencies are then divided by 2. But can’t it be a problem for the synchronization procedure of the DDS to have this kind of transient state juste after the IO_UPDATE, due to the change of frequencies of SYSCLK and SYNC_CLK ?
2. We make a SYNC_IN timing validation by use of the setup and hold validation block, and so we obtain some values for the programmable delay settings (SYNC_IN delay and validation delay). My question is: if we reset our board, or power-down then power-up it, will the SYNNC_IN delay and validation delay found before still be correct, or is a new timing validation procedure must be run each time the board is powered-up ?

Thanls a lot for your help or feedbacks !

Best regards,

Antoine