Multi Chip Synchronization using AD9528

Question

Hi, 
 We are using three AD9528 in our configuation , where one A9528 is to synchronize other two .All three AD9528's are communicating over a single SPI protocal depending on their on Chip Select . 
 We are not able to observe the change in sysref k- divider value , if we boot the FPGA by providing device clocks to the two AD9528's (other than controller AD9528) . 
 We are able to observe the device tree changes in the sysref frequency , if we disconnect device clocks to the two AD9528's and boot the board . 
 Can anyone help me out with this. 
 
 Thanks 
 Uma

pminc48 · Accepted Answer

HI, 
 I am not sure I have a clear picture of your system. If you could send me a block diagram of your system, it will help. 
 You then say that when the FPGA changes sysref K-divider value, the AD9528 does not change the SYSREF clock. Is this what you are saying? Depending the SYSREF generation mode you use, you need to create a SYSREF request signal first. See the data sheet rev F, page 24 on how to create it. 
 Petre)

pminc48 · Answer

Hi, 
 I am afraid you need to open this issue on the ADRV9009 board. It seems you are using some scripts I am do not support 
 Petre

UmaDevi821 · Answer

Thanks for your reply, 
 Here is overview of our system. 
 
 Whenever I reboot the system , all devices ( ADRV9009's) are coming up and sysref clock frequency is 7.86MHz (Device clock / 16) . After running the profile config script for ADRV9009s, the sysref clock frequency automatically changed to 3.86MHz ( Device clk / 32). 
 If I try rebooting the system by disconnecting the device clock form Top AD9528 to AD9528-1 ,we are getting sysref frequency as exactly what we expected. 
 The thing I would like to highlight is that , in the same board we communicating with three AD9528's using single SPI ,depending on their Chip select as out enable.

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Multi Chip Synchronization using AD9528

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