We are using three AD9528 in our configuation , where one A9528 is to synchronize other two .All three AD9528's are communicating over a single SPI protocal depending on their on Chip Select .
We are not able to observe the change in sysref k- divider value , if we boot the FPGA by providing device clocks to the two AD9528's (other than controller AD9528) .
We are able to observe the device tree changes in the sysref frequency , if we disconnect device clocks to the two AD9528's and boot the board .
Can anyone help me out with this.
Moved from FPGA Reference Designs to Clock and Timing on Tuesday, November 28, 2023 3:29:50 AM by UmaDevi821