I am looking for RF synthesizer with JESD204 SYSREF reclocking feature. I attached the simplified schematic to clarify my task.
There is a Clock Synthesizer with JESD204B support (HMC7044 for example) which produces the Clock and SYSREF JESD204 signals.
The schematic also contains a High-Speed JESD204B converter (AD9162 for example) which should be clocked by a high frequency signal.
The clock frequency is up to 5 GHz ant it’s out of HMC7044 possibilities. One of the solutions is to use a RF PLL-based Synthesizer.
But most of High-Speed JESD204B devises (which are Subclass 1 compliant) has strong constraints for Setup/Hold timings between the Clock and SYSREF signals.
So I am looking for RF PLL-based synthesizer which will produce high-frequency output clock and will be able to reclock the SYSREF input signal
by output clock in order to have predictable timings. I think that without reclocking it can be some timing uncertainty with the temperature / power supply changes
and power On/Off cycles (because of desynchronization of internal PLL dividers).
I know the Texas Instruments' LMX2594 device with appropriate features but it has some limitations regarding to values of PLL dividers (in SYSREF mode) and does not meet my requirements.
My question is which solutions are possible with Analog Devices products for such application?
P.S. The AD9213 High-Speed JESD204 ADC has useful "Averaged SYSREF" mode which eliminates the SYSREF Setup/Hold timing constraints,
but unfortunately most of JESD204-compliant devices has no such feature.
[edited by: BorisBree at 1:30 PM (GMT -5) on 28 Nov 2023]