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AD9546 Recommended for New Designs
The AD9546 incorporates digitized clocking technology that efficiently transports and distributes clock signals in systems. Digitized clocking allows the...
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AD9546 on Analog.com

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AD9546 - Minimize Output Shifting



		

			

									
					    Oguzhan
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Nov 7, 2023 
				
			
			
		
    

				
		
    
		    		    
		    
		    		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  AD9546 
    
    		        		    		    	
			
    Hi,
    

    While we try to provide 10MHz reference clock to AD9546 (working in active mode) from OCXO, we saw that the 1Hz outputs are shifting itself step by step.
    

    How can we minimize shifting of the 1Hz outputs?
    

    We also tried that another AD9546 (free-run mode) for the 10MHz source, but nothing changed.
    

    Below, we measured 200ns between by the time the first and the last rise edge of 1Hz output of AD9546.
    

    200ns is just a value here It could be something else, acrually,  we would like to see approx 10ns shifting in one hour. Is it possible to do that?
    

     
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Clock Generation and Distribution
                
                                                    
                 hardware
                
                                                    
                 clock and timing
                
                                                    
                 Clock Synchronization
                
                                                    
                 AD9546
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                                                                                                                        
            
				
			
            
					
      
	
      

		
		
      
					
      HI,
      

      again, please send me the json file you used for this experiment.
      

      In applications in which you need to create 1Hz clocks and the DPLL loop bandwidth is 50mHz, you need the system clock to be stabilized. We use an OCXO input (like you have). We set the AuxDPLL to lock onto the OCXO and then compensate the wonder of the system clock (which I suppose is created in your case using the 52MHz crystal resonator from the eval board) at the DPLL and TDCs.
      

      You seem to use the OCXO as the DPLL reference and use that DPLL to create the 1Hz clock. This leaves uncompensated the system clock and I do not think the DPLL locks. For this reason, the output drifts function of the DPLL trying to lock.
      

      In free run, if the system clock is compensated from the OCXO, you should have a very stable 1Hz output, albeit at a frequency slightly different from an atomic 1Hz. The error is equal to the OCXO error from its nominal frequency.
      

      Petre
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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						in reply to pminc48
					
									
        
	
        

		
		
        
					
        Hi,
        

        I attached the .json file. 
        

        In addition, please find the datasheet of OCXO that I used.
        

        My scenario is using AD9546 in actvie mode.
        

        Best regards,
        

        Oguzhan
        

        PDF
        

         1423.AD9546_setup_10MHz_In_1Hz_Out_5.json.txt
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													+1
							
			
				
									
							        
			
			
			
        •  Analog Employees  
        
            
			                            
                                                                                                                        
            
				
			
            
												
						in reply to Oguzhan
					
									
        
	
        

		
		
        
					
        HI
        

        the json file is the same as the json file you sent for the other EZ questions you have:  RE: Matching AD9546 1Hz output phase with a non-periodic trig signal 
        

        I already commented on it there. I do believe the approach you took makes for some kind of positive feedback into the DPLL and this moves the outputs.
        

        The OCXO you use is extremely stable based on data sheet you attached.
        

        

        I am curious how you measured that 200ns move you showed in your first email.
        

        Petre
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
				
						
						
				
				
		
		
        
			
		
        
	
        

        

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