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AD9546 - Minimize Output Shifting

Category: Hardware
Product Number: AD9546


While we try to provide 10MHz reference clock to AD9546 (working in active mode) from OCXO, we saw that the 1Hz outputs are shifting itself step by step.

How can we minimize shifting of the 1Hz outputs?

We also tried that another AD9546 (free-run mode) for the 10MHz source, but nothing changed.

Below, we measured 200ns between by the time the first and the last rise edge of 1Hz output of AD9546.

200ns is just a value here It could be something else, acrually,  we would like to see approx 10ns shifting in one hour. Is it possible to do that?

  • HI,

    again, please send me the json file you used for this experiment.

    In applications in which you need to create 1Hz clocks and the DPLL loop bandwidth is 50mHz, you need the system clock to be stabilized. We use an OCXO input (like you have). We set the AuxDPLL to lock onto the OCXO and then compensate the wonder of the system clock (which I suppose is created in your case using the 52MHz crystal resonator from the eval board) at the DPLL and TDCs.

    You seem to use the OCXO as the DPLL reference and use that DPLL to create the 1Hz clock. This leaves uncompensated the system clock and I do not think the DPLL locks. For this reason, the output drifts function of the DPLL trying to lock.

    In free run, if the system clock is compensated from the OCXO, you should have a very stable 1Hz output, albeit at a frequency slightly different from an atomic 1Hz. The error is equal to the OCXO error from its nominal frequency.


  • Hi,

    I attached the .json file. 

    In addition, please find the datasheet of OCXO that I used.

    My scenario is using AD9546 in actvie mode.

    Best regards,




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