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ADCLK944 Clock Buffer Load Model

Category: Datasheet/Specs
Product Number: ADCLK944


An IC chip I am designing will be made to feed a differential clock into the ADCLK944 clock buffer. I plan on using the following configuration to AC couple the clocks from the outputs of CML buffers.

I wanted to use the input termination option in this figure. 

I am trying to model the input to the ADCLK944 in my simulations to make sure I am designing my clock outputs correctly.

This is the model I am using in my simulations. I will be sending the clocks signals through impedance matched PCB traces, so that is represented by the 50Ohm resistors on the right. (vss is ground). After the 50Ohm resistors I have AC coupling capacitors (denoted C_decoup, for decoupling the DC). They will be 0.1uF. The single-ended input resistance is said to be 50 Ohms in the datasheet, which is what the two 50 Ohm resistors are. The voltage source behind the 50kOhm resistor is supposed to model the DC coupling of the common-mode Vref voltage. 

The thing that worries me though, is I am expecting a differential clock signal to look like this:


(The simulation result on the right is the differential output of my clock buffer, without the ADCLK944 load model attached)

However, my simulation results show a differential clock signal as follows:


(The simulation result on the right is the same buffer above, but connected to the load model. I'm assuming Vref = 0.65 for the purpose of illustration.)

Is this the behavior I should expect at the input of the ADCLK944 chip?

As an additional question, the Vref voltage is being set to (Vcc+1)/2. If I am using a supply of Vcc=3.3V and ground of Vee = 0V, then Vref=2.15V, right?

Thank you so much for your help,

Hyomin Ahn

  • Any help appreciated! Also, does this question look like it's under the right category?

  • Additionally, the datasheet asks for:

    1. input signal slewrate of above 1V/ns (closer to 10V/ns for low jitter).

    2. "Maintain the differential inut voltage swing from approximately 400mV p-p to no more than 3.2 V p-p.

    I assume that these numbers are to be measured at the input pins of the ADCLK944? That is, it's no use if the output of my IC chip can provide those numbers, if the loading effect of the PCB, decoupling cap, and input load effect (caps and resistances) degrade my signal.
    To illustrate, it wouldn't be enough for my output signal without the load of the ADCLK944 to provide 800mVpp of single-ended swing, if that swing is diminished down to 350mVpp single-ended with the loading effects of the ADCLK944?

  • Hi Hyomin,

    Apologies for overlooking your thread.

    The input of the ADCLK944 accepts a differential voltage swing of 0.4Vpp up to 3.4Vpp (+/- 1.7V between input pins) with a common-mode voltage min of 1.35V and max of 3.2V for Vcc = 3.3V and Vee=0.

    As for the output spec, yes, Vref is 2.15V if Vcc is 3.3V and Vee is 0V.

    I'm not sure why the input waveform is changing when connecting to the ADCLK944 model that you created.

    Best regards,


  • Hi Hyomin,

    Yes, these are measured at the input pins of the ADCLK944. You can provide an input clock to the part with a little bit higher power just to ensure that enough voltage level is being received by the part.

    Best regards,


  • Thank you for the reply. Would you say that the load model of the ADCLK944 I made is representative of what the datasheet meant?

    Best regards,


  • Also, is the "slew rate" that is defined in the datasheet the single-ended slew rate, or the differential slew rate? The differential would be twice that of the single-ended.