An IC chip I am designing will be made to feed a differential clock into the ADCLK944 clock buffer. I plan on using the following configuration to AC couple the clocks from the outputs of CML buffers.
I wanted to use the input termination option in this figure.
I am trying to model the input to the ADCLK944 in my simulations to make sure I am designing my clock outputs correctly.
This is the model I am using in my simulations. I will be sending the clocks signals through impedance matched PCB traces, so that is represented by the 50Ohm resistors on the right. (vss is ground). After the 50Ohm resistors I have AC coupling capacitors (denoted C_decoup, for decoupling the DC). They will be 0.1uF. The single-ended input resistance is said to be 50 Ohms in the datasheet, which is what the two 50 Ohm resistors are. The voltage source behind the 50kOhm resistor is supposed to model the DC coupling of the common-mode Vref voltage.
The thing that worries me though, is I am expecting a differential clock signal to look like this:
(The simulation result on the right is the differential output of my clock buffer, without the ADCLK944 load model attached)
However, my simulation results show a differential clock signal as follows:
(The simulation result on the right is the same buffer above, but connected to the load model. I'm assuming Vref = 0.65 for the purpose of illustration.)
Is this the behavior I should expect at the input of the ADCLK944 chip?
As an additional question, the Vref voltage is being set to (Vcc+1)/2. If I am using a supply of Vcc=3.3V and ground of Vee = 0V, then Vref=2.15V, right?
Thank you so much for your help,