Category: Hardware
Product Number: AD9528
I configured the AD9528 in SPI mode and there was no action on the chip after I wrote the register configuration.I am sure that my AD9528 is in SPI mode because its STATUS0 and STATUS1 are low.
I have provided here my AD9528 evaluation software stp profile and my written register data.
Of course, I personally suspect that the AD9528 has a short circuit state, but I can't judge the specific problem of the AD9528.
I hope the staff can actively discuss the topic, thank you again.
ad9528_spi_write_n(0x0000, 0x99);
ad9528_spi_write_n(0x0001, 0x00);
// usleep(1000 * 100);
ad9528_spi_write_n(0x0001, 0x20);
// IO UPDATE
ad9528_spi_write_n(0x000F, 0x01);
ad9528_spi_read_n(0x8006, 0x00);
ad9528_spi_read_n(0x8005, 0x00);
ad9528_spi_read_n(0x8004, 0x00);
ad9528_spi_read_n(0x8003, 0x00);
// ad9528_spi_read_n(0x800C, 0x00);
// ad9528_spi_read_n(0x800D, 0x00);
// PLL1 REFA(R A) divider
ad9528_spi_write_n(0x0101, 0x00);
ad9528_spi_write_n(0x0100, 0x01);
// PLL1 REFB(R B) divider
ad9528_spi_write_n(0x0103, 0x00);
ad9528_spi_write_n(0x0102, 0x01);
// PLL1 feedback divider(N1)
ad9528_spi_write_n(0x0105, 0x00);
ad9528_spi_write_n(0x0104, 0x01);
// PLL1 charge pump control
ad9528_spi_write_n(0x0107, 0x00);
ad9528_spi_write_n(0x0106, 0x0C);
// PLL1 input receiver
ad9528_spi_write_n(0x010A, 0x00);
ad9528_spi_write_n(0x0109, 0x00);
ad9528_spi_write_n(0x0108, 0x20);
// PLL2 charge pump control
printf("*********************************************PLL2 charge pump control********************************************* \n");
ad9528_spi_write_n(0x0200, 0x00); // 0xE6
// PLL2 VCO CAL feedback dividers
ad9528_spi_write_n(0x0201, 0x20); // 0x87
// PLL2 control
ad9528_spi_write_n(0x0202, 0x03); // 0x03
// PLL2 VCO control.
printf("*********************************************PLL2 VCO control.********************************************* \n");
ad9528_spi_write_n(0x0203, 0x00);
// PLL2 RF VCO divider(M1)
printf("*********************************************PLL2 RF VCO divider(M1)********************************************* \n");
ad9528_spi_write_n(0x0204, 0x04); // 0x03
// PLL2 input divider
ad9528_spi_write_n(0x0207, 0x00); // 0x01
// PLL2 feedback divider(N2)
printf("*********************************************PLL2 feedback divider(N2)********************************************* \n");
ad9528_spi_write_n(0x0209, 0x00); // 0x09
ad9528_spi_write_n(0x0208, 0x1F); // 0x09
// PLL2 loop filter control
ad9528_spi_write_n(0x0206, 0x00);
ad9528_spi_write_n(0x0205, 0x00);
//*****Clock Distrbution Control*****
Channel Output1
ad9528_spi_write_n(0x0305, 0x03);
ad9528_spi_write_n(0x0304, 0x00);
ad9528_spi_write_n(0x0303, 0x00);
// Channel Output3
ad9528_spi_write_n(0x030B, 0x03);
ad9528_spi_write_n(0x030A, 0x40);
ad9528_spi_write_n(0x0309, 0x00);
// Channel Output12
ad9528_spi_write_n(0x0326, 0x03);
ad9528_spi_write_n(0x0325, 0x00);
ad9528_spi_write_n(0x0324, 0x00);
// Channel Output13
ad9528_spi_write_n(0x0329, 0x03);
ad9528_spi_write_n(0x0328, 0x00);
ad9528_spi_write_n(0x0327, 0x00);
// Outout channel power down enable
printf("*********************************************Outout channel power down enable********************************************* \n");
ad9528_spi_write_n(0x0502, 0x00);
ad9528_spi_write_n(0x0501, 0x00);
// Ignore sync enable
ad9528_spi_write_n(0x032C, 0x00);
ad9528_spi_write_n(0x032B, 0x00);
//*****SYSREF CONTROL*****
// SYSREF pattern generator K divider
printf("*********************************************SYSREF pattern generator K divider********************************************* \n");
ad9528_spi_write_n(0x0401, 0x00);
ad9528_spi_write_n(0x0400, 0x00); // 0x40
// SYSREF control
printf("*********************************************SYSREF control********************************************* \n");
ad9528_spi_write_n(0x0403, 0x00);
ad9528_spi_write_n(0x0402, 0x00);
//*****Power-Down Control*****
// Power-down control enable
printf("*********************************************Power-down control enable********************************************* \n");
ad9528_spi_write_n(0x0500, 0x10);
ad9528_spi_write_n(0x8500, 0x10);
// // IO_UPDATE
ad9528_spi_write_n(0x000F, 0x01);
//*****PLL2 Control*****
// PLL2 VCO control
printf("*********************************************PLL2 VCO control********************************************* \n");
ad9528_spi_write_n(0x0203, 0x00);
// IO_UPDATE
ad9528_spi_write_n(0x000F, 0x01);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
// SYSREF control
printf("*********************************************SYSREF control********************************************* \n");
ad9528_spi_write_n(0x0403, 0x97);
ad9528_spi_write_n(0x0402, 0x80);
//*****Status and Status Readback5
// Status control signals
printf("*********************************************Status and Status Readback5********************************************* \n");
ad9528_spi_write_n(0x0503, 0x06);
ad9528_spi_write_n(0x0504, 0xF0);
ad9528_spi_read_n(0x8503, 0x00);
ad9528_spi_read_n(0x8504, 0x00);
ad9528_spi_read_n(0x8505, 0x00);
ad9528_spi_read_n(0x8506, 0x00);
// Status pin enable and status divider enable
ad9528_spi_read_n(0x8507, 0x00);
// Readback Registers
ad9528_spi_read_n(0x8507, 0x00);
ad9528_spi_read_n(0x8508, 0x00); // 0x18
ad9528_spi_read_n(0x8509, 0x00); // 0x04
ad9528_spi_read_n(0x800B, 0x00);
ad9528_spi_read_n(0x800C, 0x00); // 0x2B
ad9528_spi_read_n(0x800D, 0x00); // 0x02
// IO_UPDATE
ad9528_spi_write_n(0x000F, 0x01);
//*****Sync Control
// Distribution sync
printf("*********************************************Distribution sync********************************************* \n");
ad9528_spi_write_n(0x032A, 0x01);
// IO_UPDATE
ad9528_spi_write_n(0x000F, 0x01);
// Distribution sync
printf("*********************************************Distribution sync********************************************* \n");
ad9528_spi_write_n(0x032A, 0x00);
// IO_UPDATE
ad9528_spi_write_n(0x000F, 0x01);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
ad9528_spi_read_n(0x8509, 0x00);
ad9528_spi_read_n(0x8508, 0x00);
