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AD9528 SPI Not Responding and Chip working exception

Category: Hardware
Product Number: AD9528

I configured the AD9528 in SPI mode and there was no action on the chip after I wrote the register configuration.I am sure that my AD9528 is in SPI mode because its STATUS0 and STATUS1 are low.

I have provided here my AD9528 evaluation software stp profile and my written register data.

Of course, I personally suspect that the AD9528 has a short circuit state, but I can't judge the specific problem of the AD9528.

I hope the staff can actively discuss the topic, thank you again.

ad9528_spi_write_n(0x0000, 0x99);
  ad9528_spi_write_n(0x0001, 0x00);
  // usleep(1000 * 100);
  ad9528_spi_write_n(0x0001, 0x20);
  // IO UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  ad9528_spi_read_n(0x8006, 0x00);
  ad9528_spi_read_n(0x8005, 0x00);
  ad9528_spi_read_n(0x8004, 0x00);
  ad9528_spi_read_n(0x8003, 0x00);

  // ad9528_spi_read_n(0x800C, 0x00);
  // ad9528_spi_read_n(0x800D, 0x00);

  // PLL1 REFA(R A) divider
  ad9528_spi_write_n(0x0101, 0x00);
  ad9528_spi_write_n(0x0100, 0x01);
  // PLL1 REFB(R B) divider
  ad9528_spi_write_n(0x0103, 0x00);
  ad9528_spi_write_n(0x0102, 0x01);
  // PLL1 feedback divider(N1)
  ad9528_spi_write_n(0x0105, 0x00);
  ad9528_spi_write_n(0x0104, 0x01);
  // PLL1 charge pump control
  ad9528_spi_write_n(0x0107, 0x00);
  ad9528_spi_write_n(0x0106, 0x0C);
  // PLL1 input receiver
  ad9528_spi_write_n(0x010A, 0x00);
  ad9528_spi_write_n(0x0109, 0x00);
  ad9528_spi_write_n(0x0108, 0x20);

  // PLL2 charge pump control
  printf("*********************************************PLL2 charge pump control********************************************* \n");
  ad9528_spi_write_n(0x0200, 0x00); // 0xE6
  // PLL2 VCO CAL feedback dividers
  ad9528_spi_write_n(0x0201, 0x20); // 0x87
  // PLL2 control
  ad9528_spi_write_n(0x0202, 0x03); // 0x03
  // PLL2 VCO control.
  printf("*********************************************PLL2 VCO control.********************************************* \n");
  ad9528_spi_write_n(0x0203, 0x00);
  // PLL2 RF VCO divider(M1)
  printf("*********************************************PLL2 RF VCO divider(M1)********************************************* \n");
  ad9528_spi_write_n(0x0204, 0x04); // 0x03
  // PLL2 input divider
  ad9528_spi_write_n(0x0207, 0x00); // 0x01
  // PLL2 feedback divider(N2)
  printf("*********************************************PLL2 feedback divider(N2)********************************************* \n");
  ad9528_spi_write_n(0x0209, 0x00); // 0x09
  ad9528_spi_write_n(0x0208, 0x1F); // 0x09

  // PLL2 loop filter control
  ad9528_spi_write_n(0x0206, 0x00);
  ad9528_spi_write_n(0x0205, 0x00);

  //*****Clock Distrbution Control*****
  Channel Output1
  ad9528_spi_write_n(0x0305, 0x03);
  ad9528_spi_write_n(0x0304, 0x00);
  ad9528_spi_write_n(0x0303, 0x00);
  // Channel Output3
  ad9528_spi_write_n(0x030B, 0x03);
  ad9528_spi_write_n(0x030A, 0x40);
  ad9528_spi_write_n(0x0309, 0x00);
  // Channel Output12
  ad9528_spi_write_n(0x0326, 0x03);
  ad9528_spi_write_n(0x0325, 0x00);
  ad9528_spi_write_n(0x0324, 0x00);
  // Channel Output13
  ad9528_spi_write_n(0x0329, 0x03);
  ad9528_spi_write_n(0x0328, 0x00);
  ad9528_spi_write_n(0x0327, 0x00);

  // Outout channel power down enable
  printf("*********************************************Outout channel power down enable********************************************* \n");
  ad9528_spi_write_n(0x0502, 0x00);
  ad9528_spi_write_n(0x0501, 0x00);

  // Ignore sync enable
  ad9528_spi_write_n(0x032C, 0x00);
  ad9528_spi_write_n(0x032B, 0x00);

  //*****SYSREF CONTROL*****
  // SYSREF pattern generator K divider
  printf("*********************************************SYSREF pattern generator K divider********************************************* \n");
  ad9528_spi_write_n(0x0401, 0x00);
  ad9528_spi_write_n(0x0400, 0x00); // 0x40
  // SYSREF control
  printf("*********************************************SYSREF control********************************************* \n");
  ad9528_spi_write_n(0x0403, 0x00);
  ad9528_spi_write_n(0x0402, 0x00);

  //*****Power-Down Control*****
  // Power-down control enable
  printf("*********************************************Power-down control enable********************************************* \n");
  ad9528_spi_write_n(0x0500, 0x10);
  ad9528_spi_write_n(0x8500, 0x10);

  // // IO_UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  //*****PLL2 Control*****
  // PLL2 VCO control
  printf("*********************************************PLL2 VCO control********************************************* \n");
  ad9528_spi_write_n(0x0203, 0x00);

  // IO_UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);
  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);
  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);
  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);
  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);

  // SYSREF control
  printf("*********************************************SYSREF control********************************************* \n");
  ad9528_spi_write_n(0x0403, 0x97);
  ad9528_spi_write_n(0x0402, 0x80);

  //*****Status and Status Readback5
  // Status control signals
  printf("*********************************************Status and Status Readback5********************************************* \n");
  ad9528_spi_write_n(0x0503, 0x06);
  ad9528_spi_write_n(0x0504, 0xF0);
  ad9528_spi_read_n(0x8503, 0x00);
  ad9528_spi_read_n(0x8504, 0x00);

  ad9528_spi_read_n(0x8505, 0x00);
  ad9528_spi_read_n(0x8506, 0x00);
  // Status pin enable and status divider enable
  ad9528_spi_read_n(0x8507, 0x00);

  // Readback Registers
  ad9528_spi_read_n(0x8507, 0x00);
  ad9528_spi_read_n(0x8508, 0x00); // 0x18
  ad9528_spi_read_n(0x8509, 0x00); // 0x04

  ad9528_spi_read_n(0x800B, 0x00);
  ad9528_spi_read_n(0x800C, 0x00); // 0x2B
  ad9528_spi_read_n(0x800D, 0x00); // 0x02

  // IO_UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  //*****Sync Control
  // Distribution sync
  printf("*********************************************Distribution sync********************************************* \n");
  ad9528_spi_write_n(0x032A, 0x01);

  // IO_UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  // Distribution sync
  printf("*********************************************Distribution sync********************************************* \n");
  ad9528_spi_write_n(0x032A, 0x00);

  // IO_UPDATE
  ad9528_spi_write_n(0x000F, 0x01);

  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);
  ad9528_spi_read_n(0x8509, 0x00);
  ad9528_spi_read_n(0x8508, 0x00);

Parents
  • I am here to provide the REGISTER, speaking, reading and writing data, "-- -- -- -- -- -- -- -- -- -- the REGISTER VALUE -- -- -- -- -- -- -- -- -- --" is read data. I hope the printed information I provided can help us to better troubleshoot the problem together.


    ***************ad9528 start config!***************
    spi device is enabled successfully.
    ***************************[ad9528Test()]***************************
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:06
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:01
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:05
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:00
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:04
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:FF
    ****ad9528_spi_read_n:rx_data[1]:FF
    ****ad9528_spi_read_n:rx_data[2]:FF
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:03
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:02
    *********************************************PLL2 charge pump control*********************************************
    *********************************************PLL2 VCO control.*********************************************
    *********************************************PLL2 RF VCO divider(M1)*********************************************
    *********************************************PLL2 feedback divider(N2)*********************************************
    *********************************************Outout channel power down enable*********************************************
    *********************************************SYSREF pattern generator K divider*********************************************
    *********************************************SYSREF control*********************************************
    *********************************************Power-down control enable*********************************************
    *********************************************PLL2 VCO control*********************************************
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    *********************************************SYSREF control*********************************************
    *********************************************Status and Status Readback5*********************************************
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:03
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:03
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:04
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:78
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:05
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:00
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:06
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:FF
    ****ad9528_spi_read_n:rx_data[1]:FF
    ****ad9528_spi_read_n:rx_data[2]:80
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:07
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:00
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:07
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:00
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:0B
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:00
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:0C
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:2B
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:80
    ****ad9528_spi_read_n:tx_data[1]:0D
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:02
    *********************************************Distribution sync*********************************************
    *********************************************Distribution sync*********************************************
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:09
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:04
    READ REGISTER-----------------------------ad9528_spi_read_n:register ----------
    ****ad9528_spi_read_n:tx_data[0]:85
    ****ad9528_spi_read_n:tx_data[1]:08
    ****ad9528_spi_read_n:tx_data[2]:00
    ----------REGISTER VALUE----------
    ****ad9528_spi_read_n:rx_data[0]:00
    ****ad9528_spi_read_n:rx_data[1]:00
    ****ad9528_spi_read_n:rx_data[2]:18

  • Hi,

    please send me the stp file and I'll take a look.

    Petre

  • The following design changes, I used the reference input outside the ERFB 30.72Mhz,

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Input Freq: 30.72 MHz
        Rb: 1
        PFD Freq: 30.72 MHz
     - Clk In -
        Powered Down
    ------------------
    -- PLL2 --
        Input Freq: 30.72 MHz
        R2: /1
        PFD Freq: 30.72 MHz
        N2: 32
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: External SysRef
        Freq: 768.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: D1
        D1:8
        Output Freq: 122.88 MHz
     - Out 2 -
        Input Source: D2
        D2:8
        Output Freq: 122.88 MHz
     - Out 3 -
        Input Source: D3
        D3:8
        Output Freq: 122.88 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 10 -
        Input Source: D10
        D10:8
        Output Freq: 122.88 MHz
     - Out 11 -
        Input Source: D11
        D11:8
        Output Freq: 122.88 MHz
     - Out 12 -
        Input Source: D12
        D12:4
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: D13
        D13:4
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x01,		1
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x01,		1
    0x105,		0x00,		0
    0x106,		0x0C,		12
    0x107,		0x02,		2
    0x108,		0x14,		20
    0x109,		0x00,		0
    0x10a,		0x02,		2
    0x10b,		0x00,		0
    0x200,		0x00,		0
    0x201,		0x20,		32
    0x202,		0x01,		1
    0x203,		0x00,		0
    0x204,		0x04,		4
    0x205,		0x00,		0
    0x206,		0x00,		0
    0x207,		0x01,		1
    0x208,		0x1F,		31
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x00,		0
    0x302,		0x07,		7
    0x303,		0x00,		0
    0x304,		0x00,		0
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x00,		0
    0x308,		0x07,		7
    0x309,		0x00,		0
    0x30a,		0x00,		0
    0x30b,		0x07,		7
    0x30c,		0x00,		0
    0x30d,		0x00,		0
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x00,		0
    0x311,		0x00,		0
    0x312,		0x00,		0
    0x313,		0x00,		0
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x00,		0
    0x317,		0x00,		0
    0x318,		0x00,		0
    0x319,		0x00,		0
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x00,		0
    0x31d,		0x00,		0
    0x31e,		0x00,		0
    0x31f,		0x00,		0
    0x320,		0x07,		7
    0x321,		0x00,		0
    0x322,		0x00,		0
    0x323,		0x07,		7
    0x324,		0x00,		0
    0x325,		0x00,		0
    0x326,		0x03,		3
    0x327,		0x00,		0
    0x328,		0x00,		0
    0x329,		0x03,		3
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0x00,		0
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x00,		0
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0x0E,		14
    0x504,		0xF0,		240
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0x00,		0
    0x509,		0x00,		0
    </registers>
    
    <frequencies>
    30720000;30720000;30720000;768000
    </frequencies>
    

  • Hi,

    the stp file you sent does not match the photo of the AD9528 eval software configuration you sent before. I'll be commenting on the stp file you sent.

    The AD9528 requires a clock source at VCXO_IN pins. It cannot function as you have it now with this input disabled. I recommend using the 122.88MHz VCXO that comes with the AD9528 eval board.

    I created the attached stp file and I tested it on an eval board:

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Input Freq: 30.72 MHz
        Rb: 1
        PFD Freq: 30.72 MHz
     - Clk In -
        Osc Freq: 122.88 MHz
        N1: 4
        PFD Freq: 30.72 MHz
    ------------------
    -- PLL2 --
        Input Freq: 245.76 MHz
        R2: x2
        PFD Freq: 122.88 MHz
        N2: 4
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 768.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: D1
        D1:8
        Output Freq: 122.88 MHz
     - Out 2 -
        Input Source: D2
        D2:8
        Output Freq: 122.88 MHz
     - Out 3 -
        Input Source: D3
        D3:8
        Output Freq: 122.88 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 10 -
        Input Source: D10
        D10:8
        Output Freq: 122.88 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 12 -
        Input Source: D12
        D12:4
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: D13
        D13:4
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x04,		4
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x04,		4
    0x105,		0x00,		0
    0x106,		0x0A,		10
    0x107,		0x03,		3
    0x108,		0x52,		82
    0x109,		0x04,		4
    0x10a,		0x03,		3
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x04,		4
    0x202,		0x23,		35
    0x203,		0x10,		16
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x01,		1
    0x208,		0x03,		3
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x80,		128
    0x302,		0x07,		7
    0x303,		0x00,		0
    0x304,		0x80,		128
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x80,		128
    0x308,		0x07,		7
    0x309,		0x00,		0
    0x30a,		0x80,		128
    0x30b,		0x07,		7
    0x30c,		0x00,		0
    0x30d,		0x80,		128
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x80,		128
    0x311,		0x04,		4
    0x312,		0x00,		0
    0x313,		0x80,		128
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x80,		128
    0x317,		0x04,		4
    0x318,		0x00,		0
    0x319,		0x80,		128
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x80,		128
    0x31d,		0x04,		4
    0x31e,		0x00,		0
    0x31f,		0x80,		128
    0x320,		0x07,		7
    0x321,		0x40,		64
    0x322,		0x80,		128
    0x323,		0x07,		7
    0x324,		0x00,		0
    0x325,		0x80,		128
    0x326,		0x03,		3
    0x327,		0x00,		0
    0x328,		0x80,		128
    0x329,		0x03,		3
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0xA0,		160
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x86,		134
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0xEB,		235
    0x509,		0x04,		4
    </registers>
    
    <frequencies>
    122880000;30720000;122880000;768000
    </frequencies>
    

    Petre

  • Thank you very much, kind engineer.

    I did not use the AD9528 development kit, but used the AD9528 on a custom carrier.

    I have provided the schematics here, and I am using the external ZL30159 as the 30.72MHz reference signal input.Enter to REF B.

    The final output of the AD9528 is 122.88MHz and 245.76MHz.

  • Hello, please respond to my question posted on September 30, 2023 at 10:28 AM

  • Hi,

    I understand you provide at REFB=30.72MHz, single ended, ac coupled clock. What is not clear to me is what VCXO frequency you use at VCXO_IN pin.

    If you tell me this, then I can create a stp file from which you can extract the register values, write them into your AD9528 and execute the initialization procedure outlined at page 41, rev F data sheet.

    Petre

  • Hi,

    Sorry, I didn't describe my problem clearly in the last message, my VCXO_IN pin is also using 30.72MHz.

  • HI,

    I created the attached. I cannot test it on an eval board because I do not have one with 30.72MHz VCXO, but it should work.

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Input Freq: 30.72 MHz
        Rb: 1
        PFD Freq: 30.72 MHz
     - Clk In -
        Osc Freq: 30.72 MHz
        N1: 1
        PFD Freq: 30.72 MHz
    ------------------
    -- PLL2 --
        Input Freq: 61.44 MHz
        R2: x2
        PFD Freq: 30.72 MHz
        N2: 16
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 768.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: D1
        D1:8
        Output Freq: 122.88 MHz
     - Out 2 -
        Input Source: D2
        D2:8
        Output Freq: 122.88 MHz
     - Out 3 -
        Input Source: D3
        D3:8
        Output Freq: 122.88 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 10 -
        Input Source: D10
        D10:8
        Output Freq: 122.88 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 12 -
        Input Source: D12
        D12:4
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: D13
        D13:4
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x01,		1
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x01,		1
    0x105,		0x00,		0
    0x106,		0x0A,		10
    0x107,		0x03,		3
    0x108,		0x12,		18
    0x109,		0x04,		4
    0x10a,		0x04,		4
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x10,		16
    0x202,		0x23,		35
    0x203,		0x10,		16
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x01,		1
    0x208,		0x0F,		15
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x80,		128
    0x302,		0x07,		7
    0x303,		0x00,		0
    0x304,		0x80,		128
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x80,		128
    0x308,		0x07,		7
    0x309,		0x00,		0
    0x30a,		0x80,		128
    0x30b,		0x07,		7
    0x30c,		0x00,		0
    0x30d,		0x80,		128
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x80,		128
    0x311,		0x04,		4
    0x312,		0x00,		0
    0x313,		0x80,		128
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x80,		128
    0x317,		0x04,		4
    0x318,		0x00,		0
    0x319,		0x80,		128
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x80,		128
    0x31d,		0x04,		4
    0x31e,		0x00,		0
    0x31f,		0x80,		128
    0x320,		0x07,		7
    0x321,		0x40,		64
    0x322,		0x80,		128
    0x323,		0x07,		7
    0x324,		0x00,		0
    0x325,		0x80,		128
    0x326,		0x03,		3
    0x327,		0x00,		0
    0x328,		0x80,		128
    0x329,		0x03,		3
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0x28,		40
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x86,		134
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0xEB,		235
    0x509,		0x04,		4
    </registers>
    
    <frequencies>
    30720000;30720000;30720000;768000
    </frequencies>
    

    Petre

  • I'm sorry., I have realized you have the VCXO coming on the P pin, while in the stp file I have coming on the N pin because this is how we have it on the eval board. 

    Sorry for the confusion.

    Petre

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Input Freq: 30.72 MHz
        Rb: 1
        PFD Freq: 30.72 MHz
     - Clk In -
        Osc Freq: 30.72 MHz
        N1: 1
        PFD Freq: 30.72 MHz
    ------------------
    -- PLL2 --
        Input Freq: 61.44 MHz
        R2: x2
        PFD Freq: 30.72 MHz
        N2: 16
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 768.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: D1
        D1:8
        Output Freq: 122.88 MHz
     - Out 2 -
        Input Source: D2
        D2:8
        Output Freq: 122.88 MHz
     - Out 3 -
        Input Source: D3
        D3:8
        Output Freq: 122.88 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 10 -
        Input Source: D10
        D10:8
        Output Freq: 122.88 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 12 -
        Input Source: D12
        D12:4
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: D13
        D13:4
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x01,		1
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x01,		1
    0x105,		0x00,		0
    0x106,		0x0A,		10
    0x107,		0x03,		3
    0x108,		0x10,		16
    0x109,		0x04,		4
    0x10a,		0x04,		4
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x10,		16
    0x202,		0x23,		35
    0x203,		0x10,		16
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x01,		1
    0x208,		0x0F,		15
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x80,		128
    0x302,		0x07,		7
    0x303,		0x00,		0
    0x304,		0x80,		128
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x80,		128
    0x308,		0x07,		7
    0x309,		0x00,		0
    0x30a,		0x80,		128
    0x30b,		0x07,		7
    0x30c,		0x00,		0
    0x30d,		0x80,		128
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x80,		128
    0x311,		0x04,		4
    0x312,		0x00,		0
    0x313,		0x80,		128
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x80,		128
    0x317,		0x04,		4
    0x318,		0x00,		0
    0x319,		0x80,		128
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x80,		128
    0x31d,		0x04,		4
    0x31e,		0x00,		0
    0x31f,		0x80,		128
    0x320,		0x07,		7
    0x321,		0x40,		64
    0x322,		0x80,		128
    0x323,		0x07,		7
    0x324,		0x00,		0
    0x325,		0x80,		128
    0x326,		0x03,		3
    0x327,		0x00,		0
    0x328,		0x80,		128
    0x329,		0x03,		3
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0x28,		40
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x86,		134
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0xEB,		235
    0x509,		0x04,		4
    </registers>
    
    <frequencies>
    30720000;30720000;30720000;768000
    </frequencies>
    

Reply
  • I'm sorry., I have realized you have the VCXO coming on the P pin, while in the stp file I have coming on the N pin because this is how we have it on the eval board. 

    Sorry for the confusion.

    Petre

    <header>
    product = AD9528
    softwareversion = 1.0.0.3
    </header>
    
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Powered Down
     - Ref B -
        Input Freq: 30.72 MHz
        Rb: 1
        PFD Freq: 30.72 MHz
     - Clk In -
        Osc Freq: 30.72 MHz
        N1: 1
        PFD Freq: 30.72 MHz
    ------------------
    -- PLL2 --
        Input Freq: 61.44 MHz
        R2: x2
        PFD Freq: 30.72 MHz
        N2: 16
        Dist Freq: 983.04 MHz
        M: 4
        VCO Freq: 3.93216 GHz
    ----------------------
    -- SysRef --
        Source: Internal Generation
        Freq: 768.0 kHz
    ----------------------
    -- Distribution --
        Input Source: PLL2
        Input Freq: 983.04 MHz
     - Out 0 -
        Input Source: D0
        D0:8
        Output Freq: 122.88 MHz
     - Out 1 -
        Input Source: D1
        D1:8
        Output Freq: 122.88 MHz
     - Out 2 -
        Input Source: D2
        D2:8
        Output Freq: 122.88 MHz
     - Out 3 -
        Input Source: D3
        D3:8
        Output Freq: 122.88 MHz
     - Out 4 -
        Input Source: D4
        D4:5
        Output Freq: 196.608 MHz
     - Out 5 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 6 -
        Input Source: D6
        D6:5
        Output Freq: 196.608 MHz
     - Out 7 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 8 -
        Input Source: D8
        D8:5
        Output Freq: 196.608 MHz
     - Out 9 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 10 -
        Input Source: D10
        D10:8
        Output Freq: 122.88 MHz
     - Out 11 -
        Input Source: Sysref
        Output Freq: 768.0 kHz
     - Out 12 -
        Input Source: D12
        D12:4
        Output Freq: 245.76 MHz
     - Out 13 -
        Input Source: D13
        D13:4
        Output Freq: 245.76 MHz
    ----------------------
    </detailed setup information>
    
    <registers>
    Register (Hex),	Value (Hex),	Value (Dec)
    0x0,		0x00,		0
    0x1,		0x00,		0
    0x3,		0x05,		5
    0x4,		0xFF,		255
    0x5,		0x00,		0
    0x6,		0x03,		3
    0xa,		0x00,		0
    0xb,		0x00,		0
    0xc,		0x56,		86
    0xd,		0x04,		4
    0xf,		0x00,		0
    0x100,		0x01,		1
    0x101,		0x00,		0
    0x102,		0x01,		1
    0x103,		0x00,		0
    0x104,		0x01,		1
    0x105,		0x00,		0
    0x106,		0x0A,		10
    0x107,		0x03,		3
    0x108,		0x10,		16
    0x109,		0x04,		4
    0x10a,		0x04,		4
    0x10b,		0x00,		0
    0x200,		0xFF,		255
    0x201,		0x10,		16
    0x202,		0x23,		35
    0x203,		0x10,		16
    0x204,		0x04,		4
    0x205,		0x2A,		42
    0x206,		0x00,		0
    0x207,		0x01,		1
    0x208,		0x0F,		15
    0x209,		0x00,		0
    0x300,		0x00,		0
    0x301,		0x80,		128
    0x302,		0x07,		7
    0x303,		0x00,		0
    0x304,		0x80,		128
    0x305,		0x07,		7
    0x306,		0x00,		0
    0x307,		0x80,		128
    0x308,		0x07,		7
    0x309,		0x00,		0
    0x30a,		0x80,		128
    0x30b,		0x07,		7
    0x30c,		0x00,		0
    0x30d,		0x80,		128
    0x30e,		0x04,		4
    0x30f,		0x40,		64
    0x310,		0x80,		128
    0x311,		0x04,		4
    0x312,		0x00,		0
    0x313,		0x80,		128
    0x314,		0x04,		4
    0x315,		0x40,		64
    0x316,		0x80,		128
    0x317,		0x04,		4
    0x318,		0x00,		0
    0x319,		0x80,		128
    0x31a,		0x04,		4
    0x31b,		0x40,		64
    0x31c,		0x80,		128
    0x31d,		0x04,		4
    0x31e,		0x00,		0
    0x31f,		0x80,		128
    0x320,		0x07,		7
    0x321,		0x40,		64
    0x322,		0x80,		128
    0x323,		0x07,		7
    0x324,		0x00,		0
    0x325,		0x80,		128
    0x326,		0x03,		3
    0x327,		0x00,		0
    0x328,		0x80,		128
    0x329,		0x03,		3
    0x32a,		0x00,		0
    0x32b,		0x00,		0
    0x32c,		0x00,		0
    0x32d,		0x00,		0
    0x32e,		0x00,		0
    0x400,		0x28,		40
    0x401,		0x00,		0
    0x402,		0x00,		0
    0x403,		0x86,		134
    0x404,		0x04,		4
    0x500,		0x10,		16
    0x501,		0x00,		0
    0x502,		0x00,		0
    0x503,		0xFF,		255
    0x504,		0xFF,		255
    0x505,		0x00,		0
    0x506,		0x00,		0
    0x507,		0x00,		0
    0x508,		0xEB,		235
    0x509,		0x04,		4
    </registers>
    
    <frequencies>
    30720000;30720000;30720000;768000
    </frequencies>
    

Children
  • Thank you very much for your help, I have successfully run AD9528.

  • This is my modified program, I provide it here.
    printf("***************************[ad9528Test V1.0]***************************\n");
      // IO UPDATE

      ad9528_spi_write_n(0x0000, 0x99);
      usleep(1000 * 100);
      ad9528_spi_write_n(0x0001, 0x00);
      usleep(1000 * 100);
      ad9528_spi_write_n(0x0001, 0x20);
      // IO UPDATE
      ad9528_spi_write_n(0x000F, 0x01);

      ad9528_spi_read_n(0x8006, 0x00);
      ad9528_spi_read_n(0x8005, 0x00);
      ad9528_spi_read_n(0x8004, 0x00);
      ad9528_spi_read_n(0x8003, 0x00);

      // PLL1 REFA(R A) divider
      ad9528_spi_write_n(0x0101, 0x00);
      ad9528_spi_write_n(0x0100, 0x01);
      // PLL1 REFB(R B) divider
      ad9528_spi_write_n(0x0103, 0x00);
      ad9528_spi_write_n(0x0102, 0x01);
      // PLL1 feedback divider(N1)
      ad9528_spi_write_n(0x0105, 0x00);
      ad9528_spi_write_n(0x0104, 0x01);
      // PLL1 charge pump control
      ad9528_spi_write_n(0x0107, 0x03);
      ad9528_spi_write_n(0x0106, 0x0A);
      // PLL1 input receiver
      ad9528_spi_write_n(0x010A, 0x04);
      ad9528_spi_write_n(0x0109, 0x04);
      ad9528_spi_write_n(0x0108, 0x10);

      // PLL2 charge pump control
      printf("*********************************************PLL2 charge pump control********************************************* \n");
      ad9528_spi_write_n(0x0200, 0xFF); // 0xE6
      // PLL2 VCO CAL feedback dividers
      ad9528_spi_write_n(0x0201, 0x10); // 0x87
      // PLL2 control
      ad9528_spi_write_n(0x0202, 0x23); // 0x03
      // PLL2 VCO control.
      printf("*********************************************PLL2 VCO control.********************************************* \n");
      ad9528_spi_write_n(0x0203, 0x10);
      // PLL2 RF VCO divider(M1)
      printf("*********************************************PLL2 RF VCO divider(M1)********************************************* \n");
      ad9528_spi_write_n(0x0204, 0x04); // 0x03
      ad9528_spi_write_n(0x0205, 0x2A); // 0x03
      // PLL2 input divider
      ad9528_spi_write_n(0x0207, 0x01); // 0x01
      // PLL2 feedback divider(N2)
      printf("*********************************************PLL2 feedback divider(N2)********************************************* \n");
      ad9528_spi_write_n(0x0209, 0x00); // 0x09
      ad9528_spi_write_n(0x0208, 0x0F); // 0x09

      // PLL2 loop filter control
      ad9528_spi_write_n(0x0206, 0x00);
      ad9528_spi_write_n(0x0205, 0x00);

      //*****Clock Distrbution Control*****
      // Channel Output1
      ad9528_spi_write_n(0x0305, 0x07);
      ad9528_spi_write_n(0x0304, 0x80);
      ad9528_spi_write_n(0x0303, 0x00);
      // Channel Output3
      ad9528_spi_write_n(0x030B, 0x00);
      ad9528_spi_write_n(0x030A, 0x80);
      ad9528_spi_write_n(0x0309, 0x07);
      // Channel Output12
      ad9528_spi_write_n(0x0326, 0x03);
      ad9528_spi_write_n(0x0325, 0x00);
      ad9528_spi_write_n(0x0324, 0x00);
      // Channel Output13
      ad9528_spi_write_n(0x0329, 0x03);
      ad9528_spi_write_n(0x0328, 0x00);
      ad9528_spi_write_n(0x0327, 0x00);

      // Outout channel power down enable
      printf("*********************************************Outout channel power down enable********************************************* \n");
      ad9528_spi_write_n(0x0502, 0x00);
      ad9528_spi_write_n(0x0501, 0x00);

      // Ignore sync enable
      ad9528_spi_write_n(0x032C, 0x00);
      ad9528_spi_write_n(0x032B, 0x00);

      //*****SYSREF CONTROL*****
      // SYSREF pattern generator K divider
      printf("*********************************************SYSREF pattern generator K divider********************************************* \n");
      ad9528_spi_write_n(0x0401, 0x00);
      ad9528_spi_write_n(0x0400, 0x28); // 0x40
      // SYSREF control
      printf("*********************************************SYSREF control********************************************* \n");
      ad9528_spi_write_n(0x0403, 0x86);
      ad9528_spi_write_n(0x0402, 0x00);

      //*****Power-Down Control*****
      // Power-down control enable
      printf("*********************************************Power-down control enable********************************************* \n");
      ad9528_spi_write_n(0x0500, 0x10);

      // // IO_UPDATE
      ad9528_spi_write_n(0x000F, 0x01);

      //*****PLL2 Control*****
      // PLL2 VCO control
      printf("*********************************************PLL2 VCO control********************************************* \n");
      ad9528_spi_write_n(0x0203, 0x10);

      // IO_UPDATE
      ad9528_spi_write_n(0x000F, 0x01);

      // // SYSREF control
      printf("*********************************************SYSREF control********************************************* \n");
      ad9528_spi_write_n(0x0403, 0x86);
      ad9528_spi_write_n(0x0402, 0x00);

      //*****Status and Status Readback5
      // Status control signals
      printf("*********************************************Status and Status Readback5********************************************* \n");
      ad9528_spi_write_n(0x0503, 0xFF);
      ad9528_spi_write_n(0x0504, 0xFF);
      ad9528_spi_read_n(0x8503, 0x00);
      ad9528_spi_read_n(0x8504, 0x00);

      ad9528_spi_read_n(0x8505, 0x00);
      ad9528_spi_read_n(0x8506, 0x00);
      // Status pin enable and status divider enable
      ad9528_spi_read_n(0x8507, 0x00);

      ad9528_spi_read_n(0x800B, 0x00);
      ad9528_spi_read_n(0x800C, 0x00); // 0x2B
      ad9528_spi_read_n(0x800D, 0x00); // 0x02

      // IO_UPDATE
      ad9528_spi_write_n(0x000F, 0x01);

      // IO_UPDATE
      ad9528_spi_write_n(0x000F, 0x01);

      // Distribution sync
      printf("*********************************************Distribution sync********************************************* \n");
      ad9528_spi_write_n(0x032A, 0x00);
      // IO_UPDATE
      ad9528_spi_write_n(0x000F, 0x01);
      ad9528_spi_read_n(0x8509, 0x00);
      ad9528_spi_read_n(0x8508, 0x00);
  • I'm sorry, I just misread the measurements and thought I was successful.

    I was instrumented to measure the marked pins, and there was no signal output.

  • HI,

    because you do not see any outputs, it is not clear if a sync command was issued. The data sheet says such command is issued automatically after PLL2 locks. after power up. Did you get the PLL2 to lock?

    The data sheet offers a procedure to initialize the AD9528 at page 41. I am not sure you follow it. I see that you read registers 0x8509 and 0x8509, which do not exist in the AD9528. 

    Petre

  • Thank you very much for your help. I have completed the configuration of the AD9528 by referring to the chip configuration process in the document.!

  • You are great. I'm very happy you did it.

    Petre

  • Hello, engineer.,

    Can I set the waveform type in the register configuration of the AD9528?

    Both waveforms are output via the AD9528, out12 and out13.

    One of them belongs to the digital waveform of the pulse signal.

    ...

    ...

  • Hi,

    I am not sure I follow your question. You can set the outputs to be LVDS, LVDS boost or HSTL

    You are showing me a clock below100MHz (89MHz) that looks nice. Then you also show a 250MHz (?) clock that looks filtered. It may be the scope probe does not have enough bandwidth the capture that clock correctly.

    Petre

  • Hi,

    The output Settings of these two waveforms are the same, both are set to LVDS, but one is 89Mhz and the other is 245.76MHz.

    Sincere regards.