Matching AD9546 1Hz output phase with a non-periodic trig signal

HI,

the easiest approach would be to make the non periodic signal at M1 pin to work as a synchronizer of the distribution dividers. See 0x4 entry below. I looked with an oscilloscope and the 1Hz output stays high during the sync operation, so it may work

I am not sure there is any other approach.

If M1 signal was periodical, you could measure the phase offset between the the M1 clock and the 1Hz output (you would bring that 1Hz output to an input). Then you would adjust the DPLL0 phase offset (page 132 in the data sheet) and this would move the 1Hz outputs smoothly, based on the phase slew limit rate.

Or you can set DPLL0 to generate 1Hz from one of the auxiliary NCOs and you would change the Aux NCO frequency through SPI to adjust the 1Hz output. This would get rid of M1, but you would need to know the adjustment frequency of the NCO.

Petre

Hi,

I configured M-Pin as Sync All control function and it worked.

But there is an another problem.

While we are syncronizing outputs, we configured M0 Pin as “Sync All” control function (AND Invert). But the AD9546 works a bit different. In order to set the time of syncronized rising edge, AD9546 needs logic low on M0 pin and waits for approx. 3 seconds to set its outputs low and right after that it needs logic high on M0 pin to start to give syncronized 1Hz outputs. Its possible to minimize that 3 seconds?

Here I tried to explain with graphs. Basically, we want to see Figure 1 but AD9546 works like Figure2.

Figure1 : Desired scenario

 Figure2: How AD9546 actually works.

Best regards,

Oguzhan

HI,

My last answer to you from  September, I talk about the clock staying high during the sync operation. Your second figure does not show this.

Could you please send me the json file you used for these tests?

I'll take another look using your configuration and get back to you.

Petre

Hi,

Here you can find the .json file that I created and used in my tests.

AD9546_setup_10MHz_In_1Hz_Out_5.json.txt

Best regards,

Oguzhan

Hi,

first, regarding the AD9546 configuration you use: it is not good to use the REFA as both the reference clock to a DPLL and also as the reference clock to the AuxDPLL, which you then use to compensate the same DPLL. Better not enable any profile for that DPLL, so the DPLL enters in free run after power up and the output is maintained as stable as the REFA because of the AuxDPLL compensation.

Regarding the Sync All command. You are right. If you manipulate one of the Mx pins to replicate the bit 3 in register 0x2000 becoming 1, the output clock goes to low level after at least 3 clock cycles. Because in your case the clock is 1Hz, the output stops clocking after at least 3 s. Then, when the Mx pin is manipulated to make bit 3 in register 0x2000 to go back to 0, the output starts immediately to generate a clock.

Please note M0 pin cannot be used on the eval board as a control pin because there is an a c coupling capacitor on the path and the AD9546 expects a CMOS signal there. So in my tests I used M3 pin instead because that one is dc coupled into the AD9546.

You can see attached my tests.

PDF

Petre