The CLK frequency output from AD9516-1 on DAC AD9787 evaluation board 'AD9787-DPG2-EBZ', i.e., ~2440MHz, didn't match the configuration of 2560MHz by ACE.

Hi JZPS ,

Can you describe your setup for measuring the 2.44GHz VCO output? The VCO is internal to AD9787 or AD9516-1, the only indicator I see is through the registers for the PLL Band in Registers 0x04 [7:2] in AD9787

Regards,

Marco

Hi, Marco,

Thanks for taking a look for this case.

I have DAC AD9787 evaluation board with controller, and I used on board CLK from AD9516-1 as DAC CLK, and DAC PLL is not used.

When I need 600MHz DAC CLK, I set AD9516-1 VCO 2.4GHz (with external Ref 10MHz in), and then divided by 4 to get 600MHz for my DAC, as shown in attached capture in orignal post; it works fine. I can monitor 600MHz CLK with spectrum analyzer with a probe at CLK output of AD9516-1, I can also get Data CLK 150MHz with interpolation x4 in DAC.

When I want to set DAC CLK 640MHz, I set AD9516-1 VCO to 2.56GHz, and then divided by 4 with configuration from ACE, everything looks fine from configuration in ACE, it is supposed to get 640MHz DAC CLK, and 160MHz Data CLK; but I got Data CLK shown about 152MHz in DPG lite SW, and I monitor DAC CLK output from AD9516-1, it is about 610MHz instead of 640MHz. I assumed that VCO is only about 610 MHz x4 = 2.44GHz.

I have checked the registers of AD9516-1 for PLL A/B counter, i.e., 0x013/0x014, they are correctly set. 

The issue is the output CLK frequency is not as expected (configured).

Jian

Hi JZPS ,

Please give us a few days to test this on bench. Are you probing the CLK output from pin 42/43 in AD9516-1? Can you also provide a capture of DPGLite showing the 152MHz data CLK? The DCO frequency shown in DPGLite should be the fDACCLK over the interpolation factor of x4 (assuming Dual port mode).

Regards,

Marco

Hi, Marco,

I actually probe at JP6 of 'AD9787 evaluation board', as shown below, which should be the same signal from pin 42 of AD9516-1.

The spectrum captured shown below with above probe.

The DCO frequency 152.118MHz is shown in DPG Lite as below

I also noticed that AD9516 on the board cannot be identified by ACE, and when I open it, it is shown as AD9516-5 instead of AD9516-1, which is actually chip on the board. the capture is shown below.

Let me know if more info is needed.

Thanks

Jian

Hi JZPS ,

Thank you for providing these information. I've replicated this problem on bench by isolating the AD9516-1 to the AD9787 by removing connections in JP4 and JP5. Unfortunately, the problem seems to be with the AD9516-1 clock. The DACCLK output from AD9516-1 through OUT2 is not exceeding ~610MHz even if the configuration in ACE is correct. My guess is the AD9516-1 on-chip VCO is not exceeding the 2.5GHz tuning frequency. 

I will endorse this question to pminc48 who is the product owner of AD9516-1. Hopefully he will be able to answer your query (moved to Clock and Timing group)

Regards,

Marco

Thanks, Marco,

I will wait the response from JMMina, so that I could determine if I could use AD9516-1 in my design.

BR, Jian

HI,

I took an AD9516-3 eval board (I do not have an AD9516-1 eval board) and I configured it to receive a 10MHz, 3dBm reference clock at REF1 and output at OUT2 a 640MHz, LVPECL, 780mV, 4mA (default).

After I calibrated the VCO, I set the STATUS pin to output the "DLD and status selected REF and status VCO" and it turned on, meaning the PLL locked. I also checked with a scope probe and I saw STATUS pin was 3.3V.

I then put a phase noise analyzer on OUT2 and I saw a 639.999729MHz phase noise profile.

So I do believe the AD9516-1 is capable to output 640MHz or higher, up to 2.95GHz the data sheet specifies.

I looked at the AD9788 eval board schematic to see how the AD9516-1 is configured. I saw that the REF1 clock is differential (so the differential reference bit 0 in register 0x1C should be set to 1). In my case, I apply a single ended clock, but this should not be a problem.

I see the loop filter has been changed from the eval board. I introduced it into a ADIsimCLK, I configured the AD9516-1 for OUT2=640MHz and I did not see any problem. OUT2=640MHz was simulated without any problem.

I also looked at the OUT2 schematic on AD9788 eval board. It has the regular LVPECL schematic, but it has some additional circuitry for creating a common mode. I am not a specialist in the AD9787. I suppose it requires a common mode voltage. 

Marco removed JP4 and JP5 and it saw this clock "not exceeding 610MHz". This sounds to me like the PLL is not locked. Do you both do the VCO calibration on the AD9516-1? Do you get the PLL to lock? See if the STATUS pin in the condition I set goes high, indicating the PLL has locked.

Petre

Hello, Petre,

Thank you for checking into this case.

I did a quick check with my evaluation board of AD9787, and JP5/JP6 are set to use AD9516-1 on the board as clock source for DAC AD9787; I have noticed that when i set AD9516-1 VCO 2.4GHz, I got LD (LED) 'ON", and when i changed VCO to 2.56GHz, LD (LED) is 'OFF", it seems PLL not locked. 

I don't know how to calibrate VCO in my case. I think that PLL circuit works as I can set VCO 2.4GHz, but why it doesn't work with 2.56GHz, with same reference input and circuits.

In my design, I may consider to use AD9517-3 as maximum 6 outputs and 3 different frequencies would be required. I do hope to have more information which parameters could affect VCO/PLL when set different frequency. 

Best regards, Jian

Hi,

I am not a specialist in the software you use with the AD9787, so I cannot help you.

Maybe you are able to do one write command at a time into the AD9516-1. The data sheet provides this procedure to calibrate the AD9516-1:

Try implementing this sequence of write operations. This will get the AD9516-1 PLL VCO to calibrate and then lock. This will make sure the output clock is 640MHz.

Petre

Hi JZPS ,

The registers for calibrating the VCO are not accessible in the AD9516 Memory map in ACE System Explorer, because the ACE plugin is for AD9516-5 (as you pointed out). An example is Register 0x18 (PLL Control 3). Bits [2:0] cannot be configured in ACE through the Memory map.

However, you can still write to the locked out registers by utilizing Macro Tools in ACE. Guidance is in this link: Navigation [Analog Devices Wiki] under the Macro Tool section. Below is the ACE macro sequence indicated in Page 24 for your reference. Apply the 10MHz Refclk first before executing the macro sequence below. Once the sequence is done, the VCO should be calibrated and you should be able to read 160MHz DCO in DPGLite. Let me know if this works for you. 

Best Regards, Marco