HMC7044 Register set

Hi VK19,

You can use HMC7044 evaluation software to extract your register values. You can download evaluation software from the below link.

Link: EVAL-HMC7044 Evaluation Board | Analog Devices

You can use this software to set your input buffer settings, PLL1 and PLL2 configuration as well as the output network configurations. There are a couple of important points when using GUI,

1- You need to update the below registers,

2- SYSREF timer value should be integer multiple of channel divider values. 

3- I recommend setting output driver mode to LVPECL for SYSREF channels if you are using pulsed SYSREF as LVDS has problems with keeping logic 0 state at idle when using LVDS. This is not valid for continuous signals and SYSREFs. You can create a level translator circuit for the LVPECL-LVDS interface. 

As a side note, the minimum external VCO input frequency is 400MHz. If you are using 137MHz without using the internal VCO of HMC7044 (which means HMC7044 is in clock distribution mode), HMC7044 will not work as expected. If you are using PLL1 and PLL2 or just PLL2, you can use a 137MHz signal as a reference. 

I cannot create a register set file without knowing your project requirements and design. I recommend checking the evaluation software of HMC7044 to create the register settings for HMC7044. If you have any questions later on, feel free to reach out. You can share your ADISimCLK file and design requirements as well as your evaluation software output. 

Thank you so much for your reply,

external reference clock is not a problem for me ,anything is fine but output clock requirement as mentioned above.

while uploading .clk file it is showing some file format error, so i have changed file format .

Please find it below ,internal pll selection also anything is fine.

Thanks

VK19

HMC7044_CLK_Config.txt

Hi VK19,

According to your ADISimCLK file, you are using both PLL1 and PLL2. I attached a typical HMC7044 configuration for dual pll operation with your ADISimCLK configuration. You can see PLL1 and PLL2 configurations and output channel configuration, for other details you can check the datasheet. Below register settings are for typical applications. Your requirements may be different.

 DUAL_PLL_137MHZ_VCXO_137MHz_OUT.zip

Thanks,

Emrecan