hi analog team,
i am using the AD9142A evaluation board, AD9142A-M5372-EBZ with ku105 board ultra scale FPGA based board. my requirement i need to configure the ad9516-1 (14-Output Clock Generator with Integrated 2.5 GHz VCO ) , i am providing external 60Mhz clock to ad516-1 chips in the AD9142A evaluation board ,by using the ACE software i am configuring the ad9516-1 DAC clk to 1000Mhz ( out 5, out 5*) of the chip.
i am not able to configure the dac clock to 1000Mhz with in put clock of 60Mhz to J1 of Eval board , the lock detect signal is not configured properly and pll is not lock for the lock detect on the board as well as soft registor REG addr (0x01F= 0E is the dat read in the ace software , i am trying to configure this registor in sequence as show in the below
the requirment to configre the DAC and its clock:
I need to work the external 60Mhz clock to ad9516-1 devices clock as
input and generate the output5 as 1000Mhz which is dac clock, during
this process the ad95162-1 lock detect pin is not locking
reg addar[Hex] 0x01F = lock detect bit say not locked and ref1 and ref2
threshold are greater than the frequency
request to help us proper seeting of clock and DAC
Setup1 :
Request to help us in setting this configuration of AD9516
Input clock : AD9516 clk_in: 60Mhz : 7 dbm
Expected out put from the devices on to configure the clock is : 1000
Mhz on pout out 5, out5n
Request to help us in provide this configuration registers to set this
frequency
Setup2 :
Request to help us in setting this configuration of ad9142A-M5375
Dac frequency : 1Ghz
Interpolation: 4
Data bus width : word
1. Inital testing We are feeding I and Q data of 30Mhz to the DAC to see
the out put of 30 Mhz in the scope are spectrum
2. Requirement is we 225Mhz output of DAC with 10MHz band width ie 220
to 230Mhz out put is requirement
Request to help us in setting the dac configuration registers for this
above setting
requesting the analog team to help proper setting of clock as per the above requirement .
with regards
pradeep
