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not able to configure custom configuration of ad9516-1 in AD9142A-M5375-EBZ

Category: Software
Product Number: AD9142A-M5375-EBZ
Software Version: ACEInstall_1.28.3252.1429

hi analog team,

  i am using the  AD9142A evaluation board, AD9142A-M5372-EBZ with ku105 board ultra scale FPGA based board.  my requirement i need to configure the ad9516-1 (14-Output Clock Generator with Integrated 2.5 GHz VCO ) , i am providing external 60Mhz clock to ad516-1 chips in the AD9142A evaluation board ,by using the ACE software i am configuring the ad9516-1 DAC clk to 1000Mhz ( out 5, out 5*) of the chip.

i am not able to configure the dac clock  to 1000Mhz with in put clock  of 60Mhz to J1 of Eval board , the lock detect signal is not configured properly and pll is not lock for the lock detect  on the board as well as soft registor REG addr (0x01F= 0E is the dat read in the ace software , i am trying to configure this registor in sequence as show in the  below


the requirment to configre the DAC and its clock:

I need to work the external 60Mhz clock to ad9516-1 devices clock as
input and generate the output5 as 1000Mhz which is dac clock, during
this process the ad95162-1 lock detect pin is not locking

reg addar[Hex] 0x01F = lock detect bit say not locked and ref1 and ref2
threshold are greater than the frequency

request to help us proper seeting of clock and DAC

Setup1 :

Request to help us in setting this configuration of AD9516

Input clock : AD9516 clk_in: 60Mhz : 7 dbm

Expected out put from the devices on to configure the clock is : 1000
Mhz on pout out 5, out5n

Request to help us in provide this configuration registers to set this

Setup2 :

Request to help us in setting this configuration of ad9142A-M5375

Dac frequency : 1Ghz
Interpolation: 4
Data bus width : word

1.      Inital testing We are feeding I and Q data of 30Mhz to the DAC to see
the out put of 30 Mhz in the scope are spectrum
2.      Requirement is we 225Mhz output of DAC with 10MHz band width ie 220
to 230Mhz out put is requirement
Request to help us in setting the dac   configuration registers for this
above setting

requesting the analog team to help  proper setting  of clock as per the above requirement .

with regards


  • Hi,

    I'm sorry to tell you, that I do not know the AD9142A eval board to help you. You need to post this on the High Speed DAC forum, where someone will help you with it.


  • Hi  ,

    We will test this on bench and get back to you. Upon initial inspection, the PLL will lock only if the correct input frequency to J1 (REFCLK) is provided. This frequency is obtained from the 1GHz fDACCLK you require and register 0x15 (PLL Control Register). These are also provided in the Initial Configuration in ACE. Bitfield [1:0] controls the loop divider, and [3:2] controls the VCO divider. The PLL Lock range and VCO frequency is provided in Figure 55 of the datasheet (Rev A). Can you try providing an input freq of 62.5MHz to J1 and see if the PLL will lock? 



  • hi JMMina,

    i had tested with 62.5Mhz still i am not able to lock, is their any option on the AD9142A-M5372-EBZ to bypass the ad9516-1 and directly provided the clock to the dac , request to suggest any options are excat configuration values for the above thrid to test and validate the DAC output 



  • Hi  , 

    Apologies for the confusion. If you require the 1000MHz DACCLK from AD9516-1, you need to input the lower frequency from J2 in the evaluation board (AD9142A-M5375-EBZ). Unfortunately, the AD9516-1 will need to be configured as well manually in ACE through System Explorer (Reference: Navigation [Analog Devices Wiki]) because the Initial configuration Summary in ACE assumes the clock goes directly to AD9142A (i.e. bypassing clock multiplication in AD9516-1). 

    I will recommend the 2nd approach you mentioned which is to provide the clock directly to the DAC: Please refer to this link: EVALUATING THE AD9142A DIGITAL-TO-ANALOG CONVERTER [Analog Devices Wiki]. You can input the 1000MHz clock through J1 in the evaluation board, then turn off the "Enable PLL clock" in the AD9142A PLL Setup section in the Initial Configuration in ACE. 

    For further questions regarding AD9142A, please post in High-Speed DACs community.