I am using AD9528 with AD9371. My SPI of both are working fine.
AD9528 is locking its PLL but AD9371 PLL is not locking. I have checked the DEVICE Clock on AD9371 Pins. They are present. Is SYSREF mandatory for PLL locking?
AD9371
Recommended for New Designs
The AD9371 is a highly integrated, wideband RF transceiver
offering dual channel transmitters and receivers, integrated synthesizers, and digital signal...
Datasheet
AD9371 on Analog.com
AD9528
Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
Datasheet
AD9528 on Analog.com
I am using AD9528 with AD9371. My SPI of both are working fine.
AD9528 is locking its PLL but AD9371 PLL is not locking. I have checked the DEVICE Clock on AD9371 Pins. They are present. Is SYSREF mandatory for PLL locking?
Is SYSREF mandatory for PLL locking?
Yes , SYSREF should be present and going to both FPGA and AD9371