AD9528 SPI Not Responding

Hi,

your schematic does not really show where and how the SPI and RESET pins of the AD9528 are connected. It may be a matter of the protocol you implemented for the SPI.

Put the scope probes on the SPI pins of the AD9528 and verify the protocol illustrated in the data sheet is matched:

Petre

Thanks for Reply

Now SPI read is possible. There are some H/W error on my side. But On reading the 0x508 register I am getting 0xE6 instead of 0x27 

Hi,

Basically, reading the register 0x508 tells you that REFA is considered valid by the AD9528, PLL2 is locked, but PLL1 it is not. It depends on how the external VCXO is set. The schematic you posted does not show the VCXO, so I cannot say anything about it. Please attached the stp file you created with the AD9528 evaluation software to obtain the configuration you are running now on the AD9528, so I can take a look. Before designing this board, did you try the configuration on an evaluation board?

Petre

Sorry But due to some reason I can not share the STP file.

Below is my VCXO

Here is my STP file

Hi,

the VCXO schematic was blurry, so I can only make you use a 122.88MHz VCXO with a differential output. But I could not see the VCXO chip number and understand the resistors and capacitors used in the schematic. Maybe you can provide an enlarged version.

Regarding the stp file: It is not correct. Sections in red mean there is an error.

I do not know how were you able to get PLL2 locked when PLL2 VCO is set to 368.64MHz, a value outside the 3.45GHz to 4.05 GHz range.

Also, the stp file has REFA being disabled, while in your setting, you got it as being valid.

I do not know what is going on here.

I created for you a configuration that has:

REFA=30.72MHz, differential

VCXO is set as differential, but I am not sure about this. The schematic seems copied from the eval board where we use the Crystek  CVHD-950-122.880 which is a single ended, 3.3V CMOS output. Change the configuration conforming to the schematic.

I set the PLL2 with new feedback divider, VCXO doubler and charge pump current set to max, 893.5uA.

I set the dividers accordingly to the outputs I saw in your strange stp file.

I considered the 0.768MHz as SYSREF, being generated by the internal SYSREF generator. Your configuration was using the external SYSREF, which in the schematic is not connected.

3463.AD9545_setup.cso.txt

I attach the stp file I created. Take out the txt extension before loading it into the AD9528 eval software.

Petre

Thanks for your support. Now our PLL are locked and we have the desired clock coming on OUT12 and OUT13.

I am facing the same issue (spi not responding). What are the errors you had in H/W?. Maybe the error in mine is same as yours

See this issue:

 RE: SPI Port 

Petre