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AD9577 Output Enable Sequencing

Category: Datasheet/Specs
Product Number: AD9577
Software Version: N/A

Hi All

I'm currently playing about with the AD9577 and have come across some unexpected behaviour.

Does anybody know if there are any sequencing requirements on the clock outputs of the AD9577? I've run into a problem where I'm unable to utilise outputs 1 and 3 if I've disabled outputs 0 and 2 respectively. If I leave the lower numbered output of the respective VCO disabled then I appear to be able to enable / disable the respective output and set the voltage standard however it doesn't clock it just sits at a constant level. The moment I enable the lower numbered output, even if it isn't driving anything, the whole thing comes to life.

I haven't explicitly set the sync bits and according to the datasheet these should default to off.

Does anybody know what's going on? is this a undocumented feature of the chip? or simply something I haven't come across in the datasheet?

Thanks

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  • HI,

    are you playing with the eval board or you designed your own board?

    I suppose you created a configuration by using the AD9577 eval software. Could you please share the stp file?

    At page 41 in the data sheet, there is a procedure to change the default values of the registers.

    When X0[0] bit is set to 1, REFOUT is shutdown together with all the other clock outputs

    About the issues you see with enabling/disabling the outputs: you may have set the output dividers to use the same VCO dividers.

    Then, you may have powered down a channel, which includes the VCO divider. Powering down the VCO divider shut down immediately the other output as well.

    Petre

  • Hi Petre.

    Thanks for the reply.

    So I did all of my design using the datasheet. I did look at the example application but didn't find it of much use as it didn't give out register values etc just a JSON file which wasn't helpful in any way.  Yes this is on a custom board.

    I'm confident that I'm writing the registers OK as I'm getting out the correct outputs (when it's playing ball) and I can manipulate the output frequency and voltage standard as expected I has also confirmed what's being sent using a scope with decode. So I don't think it's a problem with the comms. It is however hard to exactly as the AD9577 is write only; and, as I've also found out my cost, any read operation, while supported, simply returns 0. Meaning I'm having to maintain a shadow register set to allow bit manipulation.

    As I said in my OP is haven;'t explicitly set the sync bits to sync output 0 and 1 or 2 and 3 but the behaviour I'm seeing is as you descrive as though the vco divider has been disabled the moment i power down either channels 0 or 2. But without the SyncCH01 or SyncCH23 bits set i wouldn't expect to see this behaviour as they should be running separate vco dividers.

    Hence I though I'd ask as I need to put a catch for this into my code if it is and correct what's wrong if it isn't.

    Regards

    Russell

  • HI,

    I am not sure I follow you: you say you are confident you write the registers OK, but you cannot read the registers back.

    Please try to solve this issue. Only reading back the registers you'll be confident the write operation is executed correctly. If you get outputs correctly is not a substitute for the read operation not functioning.

    Petre

  • Hi Petre

    The registers are marked in the data sheet as write only and according to this thread with a response from ADI they are indeed write only. This cost me a couple of days.....

    AD9577 I2C problem - Q&A - Clock and Timing - EngineerZone (analog.com)

    If it weren't writing then I'd have no control over the output frequency and output voltage standard but I have both.

    I'm coming to the opinion that your final clip of the datasheet is correct in all cases regardless of the SyncChXX flags (it explains the behaviour I'm seeing) even if it's not logical without output synchronisation.

  • HI,

    I'm sorry for giving you bad information. The data sheet mentions write and read operations, although the Table 32 shows only write ones. I'll make a note of this

    Please keep me posted on the developments. You seem to have solved the issue.

    Petre

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