AD9102 : can we use the same clock for several AD9102 and up to how many?

Question

Hello,

I will use up to 15 AD9102s and I would like to know if I can use the same clock for several AD9102s and up to how many?
Is there an application note that explains this?
The goal is that they have the same clock source.
Another question, the datasheet precludes the use of LVDS driver, is this obligatory because the evaluation card does not use one?

Thank you in advance for your answers. Best Regards

JMMina · Accepted Answer

Hi Sodalec , 
 Yes you can use the same Reference clock (REFCLK) for clocking several AD9102s. However, there must be a clock generator/distributor/buffer between the REFCLK and each AD9102 to prevent clock loading. 
 For the clock generator/distributor/buffer, each channel output must have the same output logic (PECL, CMOS, LVDS, etc.) so that the delay to each AD9102 would be the same. You are not required to use LVDS clock drivers. There are other configurations available for the clocking as prescribed in Figure 36-39 (page 20-21) of the datasheet . 
 On the other hand, the REFCLK must be a very low jitter, fast rise time differential signal for optimum performance of the DAC. The output voltage thresholds (Voh & Vol) of the REFCLK must be within the input voltage thresholds (Vih & Vil) of the clock generator/distributor/buffer for a certain output logic. For the clock generator/distributor, you may choose among our selections for clock generators/distributors . For the REFCLK, one example you can use is from the AX3 device family which is an ultra low-jitter clock source. Just ensure that the clock source fits the input signal level requirements of the clock generator/distributor/buffer you chose. 
 
 There is an application note for clocking several AD9102s to achieve multiple chip synchronization, however it's still in the process of getting published. But I can give you the gist: The requirements for clocking and synchronizing multiple AD9102 chips is as follows: First, careful clock distribution should be employed in the PCB layout (e.g. equal length traces) to prevent phase differences between the devices (i.e. keep the delays constant across all chips). 
 Second, pattern generation in AD9102 is signaled by the falling edge of the TRIGGER pin. Thus, the second requirement for synchronization is to ensure coincident TRIGGER edges across all the AD9102 devices. The layout above can also be applied to the TRIGGER pin PCB traces to each individual AD9102. 
 
 What is your application for using several AD9102s? There is the 12-bit AD9106 which has the same operation as the 14-bit AD9102, but it has 4 channel outputs. 
 Regards, 
 Marco)

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AD9102 : can we use the same clock for several AD9102 and up to how many?