AD9545 No Output

The config file is added here.

HI,

I studied the photos and the cso file you provided. Here are my comments:

- to set the outputs in CML mode, you need to set the P300, P301, P302, P303, P304 jumpers between pins 1 and 2

- to set the outputs in HCSL mode, you need to set the P300, P301, P302, P303, P304 between pins 2 and 3 and connect a wire between TP307 and TP308, basically connecting VOUT_COMMON to ground as it was left floating in the board design.

Make sure the 1Hz generator you use is a rubidium or Cesium based generator. Other generators are not precise enough. You say you saw REFBB LED flashing. This is not good. It should be stably green. Make sure the 1Hz is 1.2V CMOS. You may need ot take out resistor R319 because it creates a load onto the 1.2V CMOS and the clock may become not detectable by the AD9545. Put the scope probe on REFBB pin of the AD9545 at R319 to see if the high level is above 0.78V and below 1.38V according to the specification at page 12 in rev C data sheet.

I created a cso file for you with the DPLL0 and DPLL1 set in internal zero delay mode to lock onto REFBB. I had to introduce an internal 1Hz embedded clock onto OUT0B and OUT1A for the DPLLs to function. See page 89, Caveat section in rev C data sheet for the reasons.

I also set the autosync mode to immediate in Configuration Wizard. This will make the AD9545 to generate output clocks right away. You can change that later if you want otherwise. For now, keep it as such until you get the DPLLs to lock.

I set the phase slew limit rate to 2^32-1=4,294,967,295 ps/s=4.3 ms/s, the max allowed slew rate limit, so speed up the locking time. After you get used with the DPLLs locking, change it to the right slew rate for your application.

I left the phase lock threshold at 700ps. This may be too small for your case. You can increase it to 2000 ps (for example). Click Apply Changes button after you write the new value.

I recommend changing OUT0A and OUT1B into 1Hz for fun and observe the REFBB with these clocks on the scope, to see how the outputs slew towards REFBB in the lock process. Then you can change the outputs to your desired 60Hz clock and 156.25MHz.

agis4rail_petre.cso.txt

Take out the txt extension before using it into the ACE eval software.

Petre

Thank you very much, your configuration worked immediately without making any change to hardware setup(jumpers were on default positions). It was all because of the configuration that caused unstable generation of signal from the board. With your configuration, everything is good every time I measure the output signal. I wish you a nice day. 

Thank you very much, your configuration worked immediately without making any change to hardware setup(jumpers were on default positions). It was all because of the configuration that caused unstable generation of signal from the board. With your configuration, everything is good every time I measure the output signal. I wish you a nice day.