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The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
HMC7044 on Analog.com
How to determine the phase detector frequency and loop band loop bandwidth of PLL?
You can use ADISimCLK simulation to simulate and determine Phase Detector frequency and loop bandwidth.
ADIsimCLK | Design Center | Analog Devices
CLKIN3 input 10MHz clock as reference of PLL1,and VCXO is 122.88MHz ，whether this setting is appropriate。Here is the clk fileHMC7044 CLK