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Regarding single ended clock input for ADCLK854

Thread Summary

The user inquires about directly interfacing a single-ended 2Vp-p, 100 MHz, 50 ohm external clock to the CLK1 pin, as per Figure 31 in the datasheet, instead of using a 1:1 RF transformer as in the eval board schematic. The final answer confirms that direct interfacing is acceptable, provided the voltage is reduced to 1.8Vp-p using a capacitor divider to avoid turning on protection diodes and degrading jitter performance. Using a 1:1 RF transformer is also a valid option.
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Category: Hardware
Product Number: ADCLK854

Hello support team,

As per datasheet, figure 31 , it is possible to directly interface the single ended external clock to CLK1 by interfacing CLK1B to GND through cap. 

But in the eval board reference schematic, 1:1 RF transformer is being used? 

My external clock is 2 VP-P , 100 MHz , 50 ohm. Is it possible for me to directly interface the external clock to CLK1 pin as per figure 31. although there is a requirement to reduce slight voltage from 2 VP-P to 1.8 V, which I am planning to reduce it through cap. divider, or should I use 1:1 RF transformer?