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Regarding single ended clock input for ADCLK854

Category: Hardware
Product Number: ADCLK854

Hello support team,

As per datasheet, figure 31 , it is possible to directly interface the single ended external clock to CLK1 by interfacing CLK1B to GND through cap. 

But in the eval board reference schematic, 1:1 RF transformer is being used? 

My external clock is 2 VP-P , 100 MHz , 50 ohm. Is it possible for me to directly interface the external clock to CLK1 pin as per figure 31. although there is a requirement to reduce slight voltage from 2 VP-P to 1.8 V, which I am planning to reduce it through cap. divider, or should I use 1:1 RF transformer?

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  • Hi,

    Yes, you can use the input termination of Figure 31 for single-ended 1.8V CMOS and ensure that the voltage level will not exceed the maximum 1.8Vp-p as larger voltage swings can turn on the protection diodes and degrade jitter performance.

    Best regards,
    Mark

Reply
  • Hi,

    Yes, you can use the input termination of Figure 31 for single-ended 1.8V CMOS and ensure that the voltage level will not exceed the maximum 1.8Vp-p as larger voltage swings can turn on the protection diodes and degrade jitter performance.

    Best regards,
    Mark

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